Fujitsu F2 MC-8FX Family, Руководство по оборудованию, Страница: 410 / 602

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CHAPTER 22 I
2
C
22.7.1 l
2
C Interface
The I
2
C interface is an eight-bit serial interface synchronized with the shift clock. It
conforms to the I
2
C bus specification defined by Philips.
■
I
2
C System
The I
2
C bus system uses the serial data line (SDA0) and serial clock line (SCL0) for data transfers. All the
devices connected to the bus require open drain or open collector outputs which must be connected with a
pull-up resistor.
Each of the devices connected to the bus has a unique address which can be set up using software. The
devices always operate in a simple master/slave relationship, where the master functions as the master
transmitter or master receiver. The I
2
C interface is a true multi-master bus with a collision detection
function and arbitration function to prevent data from being lost if more than one master attempts to start
data transfer at the same time.
■
I
2
C Protocol
Figure 22.7-1 shows the format required for data transfer.
Figure 22.7-1 Data Transfer Example
The slave address is transmitted after a start condition (S) is generated. This address is seven bits followed
by the data direction bit (R/W) in the eighth bit position. Data is transmitted after the address. The data is
eight bits followed by an acknowledgment.
Data can be transmitted continuously to the same slave address in consecutive units of eight bits plus
acknowledgment.
Data transfer is always ended in the master stop condition (P). However, the repeated start condition (Sr)
can be used to transmit the address which indicates a different slave without generating a stop condition.
SDA0
SCL0
R/W
LSB MSB MSB LSB
Start
condition (S)
7-bit address
Acknowledge bit
8-bit data
No acknowledge
Stop
condition (P)