Fujitsu F2 MC-8FX Family, Руководство по оборудованию

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CHAPTER 16 8/16-BIT COMPOSITE TIMER
16.5.1 8/16-bit Composite Timer 00/01 Control Status Register 0
(T00CR0/T01CR0)
The 8/16-bit composite timer 00/01 control status register 0 (T00CR0/T01CR0) selects the
timer operation mode, selects the count clock, and enables or disables IF flag interrupts.
The T00CR0 and T01CR0 registers correspond to timers 00 and 01, respectively.
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8/16-bit Composite Timer 00/01 Control Status Register 0 (T00CR0/T01CR0)
Figure 16.5-2 8/16-bit Composite Timer 00/01 Control Status Register 0 (T00CR0/T01CR0)
F2
F1 F0
Timer operation mode select bits
0 0
0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
IFE IF flag interrupt enable
0
IF flag interrupt disabled
1 IF flag interrupt enabled
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 Initial value
IFE C2 C1 C0 F3 F2 F1 F0 00000000
B
R/W R/W R/W R/W R/W R/W R/W R/W
R/W : Readable/writable (Read value is the same as write value)
R : Read only
: Initial value
F3
0
0
0
0
0
0
0
0
0 0
0
0 0 1
0 1
0
0 1 1
1 0 0
1 0
1
1 1 0
1 1 1
1
1
1
1
1
1
1
1
C2 C1 C0
Count clock select bits
0 0
0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
External clock
Interval timer (one-shot mode)
Interval timer (continuous mode)
Interval timer (free-run mode)
PWM timer (fixed-cycle mode)
PWM timer (variable-cycle mode)
PWC timer (H pulse = rising to falling)
PWC timer (L pulse = falling to rising)
PWC timer (cycle = rising to rising)
PWC timer (cycle = falling to falling)
PWC timer (H pulse = rising to falling; Cycle = rising to rising)
Input capture (rising, free-run counter)
Input capture (falling, free-run counter)
Input capture (both edges, free-run counter)
Input capture (rising, counter clear)
Input capture (falling, counter clear)
Input capture (both edges, counter clear)
1/2
7
x Fch
1/32 x MCLK (machine clock)
1/16 x MCLK (machine clock)
1/8 x MCLK (machine clock)
1/4 x MCLK (machine clock)
1/2 x MCLK (machine clock)
1 x MCLK (machine clock)
Address
0F92
H
T01CR0
0F93
H
T00CR0