Fluke 2680A, Руководство по обслуживанию

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268XA
Service Manual
2-14
Totalizer Input
The Totalizer Input circuit consists of Input Protection, a Digital Input Buffer circuit, and
a Totalizer Debouncing circuit. The Digital Input Buffer for the Totalizer is protected
from electrostatic discharge (ESD) damage by R31 and C48. Refer to the detailed
description of the Digital Input Buffer circuit for more information. U1 and U18 provide
input buffering for the Totalizer. The output from U18 goes to the debounce PLD; U3
The Totalizer Debounce circuit in the PLD (U3) allows the microcontroller to select
Totalizing of either the input signal or the debounced input signal. The buffered Totalizer
Input signal (TOT_IN) goes into the PLD at U3 Pin 13.
U3 Pin 9 is the debounce enable control signal, it is active high ( HI = Totalizer
Debounced, Lo = Totalizer NOT Debounced). The Totalizer output from the PLD is on
U3 Pin 23 and this signal goes to the microcontroller (CIN U4 Pin 2). The PLD receives
its clock from the microcontroller on Pin 2. The clock frequency is approximately 8 kHz.
The signal debouncer is set to approximately 1.75 ms meaning a pulse of less then 1.75
ms will not pass through. In debounce mode, the maximum repetitive frequency of the
Totalizer signal is approximately 500 Hz. In non-debounce mode, the maximum
repetitive frequency of the Totalizer is approximately 5kHz.
Inside the PLD, the Totalizer signal is routed to a MUX/DEMUX circuit and from there,
to a 3-stage shift register. The microcontroller provides an 8kHz clock signal to the PLD
(which is divided down to 2 kHz internally). The 2 kHz signal is used to clock the shift
register which produces a pulse every 2 ms (500 Hz). This pulse is then compared against
the Totalizer signal itself. If the pulse duration of the Totalizer is greater then 1.75 ms,
the Totalizer signal is passed to the output of the PLD (U3 Pin 23). If the duration of the
Totalizer signal is less then 1.75 ms, it is removed (debounced). Selection of either
“debounced” or “non-debounced” input is controlled by the DEBOUNCE_EN control
signal (U3 Pin 9). Debounce is selected when DEBOUNCE_EN is high.
From the PLD, the signal (TOTAL) is routed to a 16 bit counter in the microcontroller
(CIN U4 P2). The Totalizer counter is a 32 bit counter using a combination of the internal
counter and a 16-bit storage register internal to the microcontroller.
Totalizer Enable
Operation of the Totalizer is controlled by the TOT_ENABLE signal. The Totalizer
Enable circuit consists of Input Protection, a Digital Input Buffer circuit. The Digital
Input Buffer for the Totalizer Enable is protected from electrostatic discharge (ESD)
damage by R32 and C49. Refer to the detailed description of the Digital Input Buffer
circuit for more information.
The Totalizer Enable signal is active high. Applying a logic low to TOT_ENABLE will
disable counting by the Totalizer. TP_ENABLE* is the control signal to the
microcontroller (U4 Pin 8); Totalizer counting is enabled when this signal is held low.
A/D Theory of Operations
A/D Converter PCA Block Description
The following paragraphs describe the major blocks of circuitry on the A/D Converter
PCAs (FAI and the PAI).