Fluke 2680A, Руководство по обслуживанию

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268XA
Service Manual
2-8
rx0
Rx FIFO
uar
tclk
b
us_error
ser
vice_queue
guard_irq*
data
Address Decode
Data Mux
Trigger In/Out
Entity
addr
ce* oe*
we
*
r_w
e
y
edk
T
rig In
T
rig CPU T
rig Out
k
e
ypad_irq*
URT URT URT
Guard xing
Clock
Generator
Keypad
key_ck
URT URT URT
Tx FIFO Rx FIFO Tx FIFO Rx FIFO Tx FIFO Rx FIFO Tx FIFO Rx FIFO Tx FIFO Rx FIFO Tx FIFO
tx0 rx1 tx1 rx2 tx2 rx3 tx3 rx4 tx4 rx5 tx5 g
rd_c
k0
g
rd_c
k0*
g
rd_c
k1
g
rd_c
k1*
g
rd_c
k2
g
rd_c
k2*
g
rd_c
k3
g
rd_c
k3*
g
rd_c
k4
g
rd_c
k4*
g
rd_c
k5
g
rd_c
k5*
peup_c
k
peup_c
k*
e
wr1
e
wr1
e
wr2
e
wr3
e
wr4
e
wr5
alg109f.eps
Figure 2-4. FPGA Block Diagram
Other Bus Devices
The microprocessor’s external bus controller, in addition to the fpga, communicates with
onboard SDRAM, onboard flash ROM and PCMCIA flash memory cards. These
additional device interfaces are contained on page 4 of the 1004 schematic. There are 32
MB of onboard SDRAM, configured as 4-8 MB by 8 bit wide devices (U18, 19, 21 and
22). The timing of the row and column address strobes (RAS*, CAS*), chip select
(CS1*), write enable (RAMWE*), and byte mask signals (BSA0*-3*) is controlled by a
state machine in the microprocessor’s SIU. The relative states of these signals determine
what mode the SDRAM operates in, 4 word burst, single word access, refresh, etc. There
are 4 MB of onboard flash ROM, configured as a single 2 MB by 16 bit wide device
(U20). U20 is an Intel Strataflash E28F320J3A.