Fluke 2680A, Руководство по обслуживанию

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Theory of Operation
Introduction
2
2-7
FPGA
The gate array (U25) in the 268XA is an Altera ACEX series EP1K100QC208-1. It is on
page 5 of the 1004 schematic. It has 48Kbits of embedded dual port RAM configurable in
12 blocks of various width/depth combinations, as well as approximately 100K gates.
This design uses about 55 % of the logic cells, and about 25 % of the memory bits, spread
out over all 12 blocks, and has a maximum clock frequency of 57.4 MHz. The core runs
off of a 2.5 V linear regulator from Vcc, while the I/O pins are powered directly from
Vcc (+3.3 V).
This FPGA’s main function is performing the guard crossing communications for the 6
module slots in the 268XA chassis. The guard crossing uses a 120KBaud UART protocol
with 1 start bit, 8 data bits, 1 even parity bit and 1 stop bit. The architecture inside the
fpga is highly parallel, each module slot has its own dedicated UART, transmit FIFO,
receive FIFO, status and control registers, and interrupt flag.
The transmit FIFO is 2 bytes wide and 3 bytes deep (6 bytes total), the length of 1 guard
crossing command frame. The receive FIFO is also 2 bytes wide but is 256 bytes (512
bytes total). Each receive buffer can hold 1 complete scan’s worth of data, with all
channels configured, before it needs to be read. The status and control registers serve to
mask off or enable certain conditions for interrupt to the microprocessor.
The interface to the microprocessor is a 16 bit bi-directional data bus, a 5 bit address, a
chip select, read and write enables, a single interrupt line (GRD_IRQ*) and a 6 bit
service queue port. When the condition set by the control/status registers becomes valid,
the corresponding service queue bit will be set high. The interrupt is the NOR of all the
service queue bits. The status/control registers occupy 1 address location per module slot,
as do the Rx/Tx FIFOs. See the FPGA design description document, and Figure 2-4 for
more details.
The other main entity in the fpga is the keypad scanner. This has its own interrupt
(KEY_IRQ*), the keypad state register (8 bits wide) is memory mapped along with the
guard crossing registers, the FPGA design description document has the details of the
keypad scanner functionality.
In addition to these 2 entities, the guard crossing and the keypad scanner, the fpga
contains a clock generation circuit for the display and the in-guard power supplies, as
well as the trigger out pulse generator. These items are covered in other sections of this
document.