40
The following notes apply for these timing diagrams
•
CLK0 is the camera link output clock
•
Empty is the signal from the FIFO that starts the state machine operation in these simplified state
diagrams. The actual verilog code used a combination of Empty and other conditions to insure that
the FIFO did not under-run.
•
State [7:0] signal uses mnemonics to indicate the state machine states. The state machine starts in
Idle, changes to RD_1
st
(first FIFO read) and then loops reading the FIFO and outputting data until
the Lval signal from the FIFO deasserts.
•
The FIFO was split into 5 separate FIFOs each with their own read control signals. The five FIFOs
contain pixels 1-2, 3-4, 5-6, 7-8, 9-10. The data from the FIFOs was shown here as a byte per
pixel, so signal FIFO_d12[15:0] represents pixel2 on bits [15:8] and pixel1 on bits [7:0]
•
Signal FF_RDxx are the FIFO read signals.
•
Signal ff_lval is the Lval status out of the FIFO.
•
Signals FIFO_dxx[15:0] are the pixels from the FIFO.
•
Mux1_sel [2:0] controls the mux selects for muxs 1, 2. Mux2_sel controls muxs 3,4,etc. Thus a mux
select index of 0x0 for muxs1, 2 selects the first pixel from the two muxs which are pixels 1 and 2.
•
Signals MuxX_d show the pixels selected from the mux
20.3. 1 Tap mode
When the FIFO deasserts empty the state machine starts with a pre-read of the whole FIFO during which
pixels 1-Ten are read. The state machine then continues in a 10 cycle loop until the end of the line is
detected (ff_lval deasserted). The outputs from muxs 1, 2 are multiplexed again onto the single output tap
(data_pipe1)
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