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The following diagrams show simplified state diagrams used to design the Camera Link output stage of the
DataFPGA.
The data from the FIFOs are fed to 5-to-1 muxes on order to limit the fanout of the data from the FIFO.
There are 8 muxs in order to support 8 Tap mode. Muxs 1,3,5,7 multiplex between pixels 1,3,5,7,9 and
Muxs 2,4,6,8 multiplex between pixels 2,4,6,8,T. There are 4 mux select buses which control Muxs 1-2, 3-4,
5-6, 7-8.
The ordering of the pixels output each clock vary per the number of taps:
# of Taps Order of the pixels
output at each clock
cycle Pixels read during the current clock cycle to be
available for on subsequent clock cycles
1 Tap
1
2
3
4
5
6
7
8
9
T 1 2 3 4 5 6 7 8 9 T (whole FIFO preread)
1 2 3 4 5 6 7 8
9 T
2 Taps
1 2
3 4
5 6
7 8
9 T 1 2 3 4 5 6 7 8 9 T (whole FIFO preread)
1 2 3 4 5 6 7 8
9 T
4 Taps
1234
5678
9T12
3456
789T 1 2 3 4 5 6 7 8 9 T (whole FIFO preread)
1 2 3 4 5 6 7 8
9 T
1 2 3 4 5 6
7 8 9 T
8 Taps
1 2 3 4 5 6 7 8
9 T 1 2 3 4 5 6
7 8 9 T 1 2 3 4
5 6 7 8 9 T 1 2
3 4 5 6 7 8 9 T 1 2 3 4 5 6 7 8 9 T (whole FIFO preread)
1 2 3 4 5 6
1 2 3 4 7 8 9 T
1 2 5 6 7 8 9 T
3 4 5 6 7 8 9 T
1 2 3 4 5 6 7 8 9 T
10 Taps
1 2 3 4 5 6 7 8 9 T 1 2 3 4 5 6 7 8 9 T (whole FIFO preread)
1 2 3 4 5 6 7 8 9 T