FastVision FastCamera13, Руководство пользователя, Страница: 33 / 52

33
19.2. Video Data path overview
The DataFpga accepts video data from the sensor and formats it for transmission over the Camera Link
outputs or USB interface. The ControlFPGA controls the sensor data output and sends Lval (line valid) and
Fval (frame valid) signals to the DataFPGA. The data from the sensor is valid when Lval and Fval are
asserted. Data progresses through to the FIFO (or output to the DDR FPGA in memory mode) at the pixel
rate of the sensor and is the width of the sensor data (100 or 160 bits wide).
The video data from the sensor is sent to the DataFPGA over the HSD[47:0] and Mvdata[99:96] signal
lines. The MV13 sensor clocks out ten 10bit pixels (100 bits total) each clock (at 66Mhz) and the MV40
sensor clocks out sixteen 10bit pixels (160 bits total) each clock (60Mhz).These data lines are multiplexed
to the DataFPGA over the HSD (high speed data) signal lines at 2x the pixel rate in order to reduce the I/O
count needed by this FPGA. The DataFPGA demultiplexes this data and synchronizes it with the non
multiplexed data from the sensor and the control signals from the ControlFPGA.
The video data is then sent into the vertical binning module. This module accumulates the programmed
number of rows of video data and then forwards the binned row of data to the horizontal binning module. If
vertical binning is active then the frame height is reduced by the binning factor. The vertical binner
produces 140 bits of video data as ten 14bit pixels. The horizontal binning module adds together the
programmed number of pixels and then forwards the reduced row of data to the FIFO input mux. The
horizontal binner produces 180 bits of data as ten 18bit pixels. The FIFO input mux selects either the upper
or lower 16bits from each 18 bit pixel based upon the binning multiplier mode selection (also known as
Sensor Resolution). The video data is then stored in a large FIFO along with the state of Lval/Fval for each
block of ten (or 16) pixels.
The section of the FPGA that reads the video data from the FIFO operates at the specified Camera link
clock rate. This rate can be selected to be 33, 42.5, 66 or 85Mhz. The output state machine controls the
reading of the FIFO and outputting the data to the camera links based upon the selected number of
Camera Link taps and the pixel width selected. There are a multitude of Camera Link modes supported by
this camera, from basic one tap mode up to ten tap 80bit mode.
The output stage over the Camera Link does not use the Dval signal as defined within the Camera Link
specification. This is done to insure compatibility with a variety of framegrabbers. In order to do this, the
output state machine waits until enough data has been accumulated in the FIFO in order to not under-run
the FIFO while the line of video data is being output. This is only a concern at higher output modes like 8 to
10 tap modes running at 66 or 85Mhz Camera Link output clock speeds. This does not affect the maximum
frame rate achievable by this camera, it just insures that once Lval is asserted out the Camera Link the
whole line of data will be output without gaps.
19.3. Operating mode control overview
The operating state of the DataFPGA is set by the ControlFPGA or by the host via the serial interface. The
ControlFPGA can load stored camera configurations from the system flash memory at powerup or when
directed to load different configurations by the host.
19.4. Camera State
Internal to the ControlFPGA all the camera state is saved in a Block RAM. Copies of the current state can
be saved to the flash or uploaded to the host. The current state can also be retrieved from flash or
changed by the host. Only the host has random access to the camera state and this only when setting
state. Reading back the camera state always sends the entire state to the host. Table 4 shows the layout
of the camera state memory. Except for sensor reference voltages, multibyte values are little endian. The
values shown in bold apply to the DataFPGA and the values shown in grey apply to the ControlFPGA.
Byte Offset (decimal) Bytes Description
0 4 C3, 5A, F0, 69 for detecting uninitialized buffers
4 2 Vln2: 14 D9
6 2 Vref1: 14 D9
8 2 Vtest: 20 00
10 2 Vref2: 23 E0