FastVision FastCamera13, Руководство пользователя, Страница: 28 / 52

28
4 Serial trigger. Must be toggled in software to trigger the sensor control logic in response to
a serial trigger command.
3 Reserved.
2 Calibrate sensor. This is a pulsed signal that schedules a calibration when this bit is
written to 1. Writing this bit to zero has no effect. Actual calibration may happen much
later, since the sensor control logic schedules calibration only between frames.
1 Sensor standby. Setting this bit to one places the sensor in low-power standby mode.
0 Dark offset enable. Setting this bit allows the sensor to apply internal calibration factors to
reduce fixed column noise.
0xFB Address Extensions. Bits 3 through 7 are reserved. Other bits are:
2,1,0 Banking bits. These bits form the two high address bits to the 1K byte data RAM, except
during register access. During register access the high bits are fixed at 6, thus register
writes are always shadowed in the 7
th
of 8 banks, allowing readback of registers that don’t
have separate read functionality from the shadow RAM. When bank 0 is selected, sensor
register write is enabled.
0xFC Serial to FPGA and Serial Status. When written, this register causes a byte of data to be
transmitted to the Data FPGA. On reads Bits 0 through 6 are reserved. Other bits are:
7 Transmitter to FPGA ready for data.
6 Transmitter to FPGA overrun error. Set if write was attempted when the transmitter wasn’t
ready for data. Cleared when the next data is written when the transmitter is ready for data.
0xFD UART to/from Camera Link. Writing this location sends a byte of serial data to the framegrabber.
Reading gets a byte of serial data and acknowledges its receipt. See the status bit descriptions
below for more information.
0xFE DAC and Flash Control / Flash and UART Status. Bits are:
7 Reserved on write, RxData Available on read. When this bit is 1, there is data available to be
read from the UART via register 0xFD. The validity of the current data depends on the error
bits listed below. This and other receive status bits are cleared when the UART is read.
6 “Fget8” on write, Transmitter Ready on read. Writing this bit to one starts the sequencer for
speeding up flash read and FPGA configuration write. Writing this bit to zero has no effect.
When 1 this bit indicates that the UART is ready to accept a byte of data to transmit to the
framegrabber.
5 DAC chip select on write, Receiver framing error on read. DAC chip select is asserted high.
This bit is inverted before driving the chip’s active low pin. Receiver framing error indicates
that a zero was detected in the stop bit position. This condition is cleared when the UART is
read.
4 DAC serial clock on write, Receiver overrun error on read. DAC serial clock runs directly to
the DAC chips. Receiver overrun indicates that a new character came in when the previous
character had not been read. In this case the older data is lost and the data in the UART is
the one causing the overrun, i.e. the most recent character received. This condition is cleared
when the UART is read.
3 Flash chip select on write, Transmit overrun on read. Flash chip select is asserted high. This
bit is inverted before driving the chip’s active low pin. Transmit overrun is set if a write was
attempted when the transmitter wasn’t ready for data. This condition is cleared when data is
written to the UART and the transmitter is ready for data.
2 Flash reset on write, transmitter empty on read. Flash reset is asserted high. This bit is
inverted before driving the chip’s active low pin. Transmitter empty is active when no data
transmission is pending. This must be checked before changing the baud rate to ensure any
pending characters finish transmitting at the current baud rate.
1 Flash serial clock on write, Flash ready on read. These correspond directly to the flash pin
functions.
0 Shared Flash and DAC serial data in on write, Flash data out on read. These correspond
directly to the respective pin functions.