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Serial Commands
Commands from the host are buffered and passed to the Data FPGA on the FPGA_CTL3 wire. The Data
FPGA therefore receives all commands from the host and can act on them accordingly. This allows
extensions to be made to the command set for Data FPGA use. To reduce logic in the Data FPGA, each
character is buffered and retransmitted at 66 MHz, synchronous to the FPGA_SYSCLK. In this way the
data FPGA doesn’t need to know about baud rate and can start up monitoring commands even before it
receives the camera state data.
Flash Data
In addition to forwarding commands from the host, the Control FPGA also uses the FPGA_CTL3 wire to
send camera state data when the Restore Camera State From Flash command is received. It also uses
the FPGA_CTL3 wire to send camera state data and Data FPGA initialization data from flash to the Data
FPGA when the Initialize FPGA From Flash command is received. The Control FPGA only responds to the
host after it has completed the required data transfer(s). The host must always wait until it receives the
response before sending another command.
When transmitting camera state data to the Data FPGA, the Control FPGA uses the same syntax as the
Set Camera State command with the starting address set to zero and a data length of 512.
When transmitting Data FPGA initialization data to the Data FPGA, the Control FPGA uses the same
syntax as the Set Camera State command with the starting address set to all ones (65,535) and a data
length as set in the Page Zero Flash Header. If the header indicates a zero data length, or the initialization
data does not start with 3C A5 0F 96, the Control FPGA will not send this command.
Serial Responses
Normally the data sent to the Data FPGA from the Control FPGA is limited in bandwidth at the source,
either by the host serial baud rate or the flash memory read rate. Response data from the Data FPGA,
which always gets forwarded to the host, must be sent at the host baud rate. To reduce the redundant logic
requirement in the Data FPGA, the Control FPGA uses the FPGA_DDRCLK wire to send a baud rate pulse
train. This signal is high for one cycle of FPGA_SYSCLK once per serial link bit period. The Data FPGA
then uses this as a shift enable for its response transmitter.
Serial response data from the Data FPGA is forwarded to the host directly by ANDing with the serial
response data from the Control FPGA. For this reason it is especially important that the host does not send
a new command before the previous command response has been received.
18. EMBEDDED SOFT PROCESSOR CORE
The Control FPGA includes a “PicoBlaze” 8-bit controller core, programmed in assembly language that
takes care of most low-speed complex operations. This soft processor handles serial protocol, flash
memory, FPGA configuration, and power-on initialization. The architecture of this core is Harvard, using a
1K by 18-bit wide instruction memory composed of 5 block RAMs, and a 1K by 8-bit wide data memory
composed of four block RAMs. The core was designed and optimized to run in the Virtex 2 series of Xilinx
FPGA’s and then adapted for the Spartan 2. It therefore is not very fast. In the MV13 it runs at 33 MHz
and in the MV40 it runs at 25 MHz (1/2 the pixel clock rate). The instructions run in a fixed 2-cycle period
with essentially no pipelining. This simplifies instruction sequence timing calculations.