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38

20. FRAME 

RATES. 

The actual Frame rate of the camera is determined by settings within the ControlFPGA and the DateFPGA. 
The ControlFPGA settings determine the data rate from the sensor by adjusting the ROI (Region of 
Interest), exposure rate and exposure delay. The DataFPGA settings determine the binning settings(which 
can increase frame rate as there is less data to send over the Camera Link Interface), the Camera link 
mode and clock speed. To get the fastest frame rate possible for a given ROI you can calculate the 
minimum required Line Period (in pixels clocks) by the following formula. 

Min Line Period =  

((Time_required_over_Camera_Link – Time_to_gather_data_from_sensor) / 1/66Mhz) – 132 (clocks per 
line) 

The time required to send each row of data over the Camera Link is calculated by: 

Time_required_over_Camera_Link  =  

(Num_Data_pixels_per_row / Num_Taps ) * 1/Selected_Clock_rate 

The time required to gather each row of data from the sensor is calculated by: 

Time_to_gather_data_from_sensor  = 132 (clocks per row min) * 1/66Mhz = 2us 

Num_Data_pixels_per_row = 

(((# of cols in ROI * 10pixels/column) / Horiz_binning) / Vertical_binning) 

So for example, when running full resolution (1280 pixels per row), no binning, in 1Tap mode at 33Mhz 
clock rate the calculation is: 

Time_required_over_Camera_Link – 2us / 1/66Mhz) – 132 (clocks per line) 

 

38.7us – 2us / 1/66Mhz = 2422 – 132 = 2290 

Thus the Minimum line period needs to be set to 2290, which adds that many clocks per line read from the 
sensor, which results in a frame rate of 1/(1024 rows * 38.7us per row) or about 25 full resolution frames 
per second. 

If we up the clock rate over the Camera Link to 85Mhz and switch to 8Tap mode then the limiting factor 
becomes the time to gather the data from the sensor:  

Time_required_over_Camera_Link  = 1280/8 * 1/85Mhz = 1.88uS 

The time duration of 1.88uS to output the line is less than the time required to gather the sensor data of 
2uS so we do not need to extend the line length and the Minimum Line period can be set to 0. 

20.1. Memory 

Operation. 

The FC13 DataFPGAa connects to the DdrFPGA via a high speed SERDES link. This link is 13 bits wide 
and is able to transmit 104 bits of data to the DdrFPGA at the sensor clock speed (66Mhz). This data path 
consists of 100 bits of data (10, 10bit pixels), 2 bits of control (Lval, Fval), and 2 spare bits. 

 

20.2. 

DATA FPGA Technical Details. 

 

Содержание FastCamera13

Страница 1: ...FASTCAMERA SERIES FASTCAMERA13 USER S MANUAL FVM 50013...

Страница 2: ...ary 20 2003 1 1 March 26 2003 1 2 March 30 2003 1 3 April 9 2003 2 0 August 10 2004 3 0 August 13 2004 4 0 August 17 2004 Trademarks FastVision is a registered trademark of FastVision LLC Channel Link...

Страница 3: ...8 Pixel Gain and Offset____________________________________________ 8 13 9 Memory Option_________________________________________________ 9 13 9 1 FIFO memory mode ____________________________________...

Страница 4: ...________________________________________________ 20 38 20 1 Memory Operation ________________________________________________20 38 20 2 DATA FPGA Technical Details ____________________________________...

Страница 5: ...HNICAL SUPPORT________________________________ 25 50 25 1 Contacting Technical Support_______________________________________25 50 25 2 Returning Products for Repair or Replacements __________________...

Страница 6: ...era The camera is designed to support many different applications by customization of the programmable logic in the camera FastVision or the customer can customize the size and content of the FPGAs an...

Страница 7: ...ard processing Supported by a full range of software tools Binning in order to achieve increased sensitivity at full frame rates Optional SRAM for ultra fast processing Optional additional DDRAM and i...

Страница 8: ...5m m 74 0mm 0 ref 7m m 132m m 12 7mm 7mm 0 ref 0 ref 39 5m m 79 0m m J3 J2 P2 FastCamera13 Front View FASTCAMERA13 CASE AND MOUNTING DIMENSIONS FastCamera13 Side View FastCamera13 Back Panel FastCame...

Страница 9: ...17 CL1_TXOUT2P 5 CL1_TXCLKOUTN 18 CL1_TXCLKOUTP 6 CL1_TXOUT3N 19 CL1_TXOUT3P 7 SERTCP 20 SERTCN 8 CC1N 21 SERTFGP 9 CC2P 22 CC1P 10 CC3N 23 CC2N 11 CC4P 24 CC3P 12 SERTFGN 25 CC4N 13 Ground 26 Ground...

Страница 10: ...ure The camera can be read out with 1 2 or 3 camera links the serial port for the really patient or via the USB port Only image data from the selected ROI is sent The camera can be configured to read...

Страница 11: ...d CL2_B 7 0 G odd CL2_C 7 0 B odd Six Taps 8 bits Color Medium 12 CL1_B 1 0 CL1_A 7 0 R even CL1_B 5 4 CL1_C 7 0 G even CL2_C 1 0 CL2_B 7 0 B even CL2_C 4 5 CL2_A 7 0 R odd CL3_C 1 0 CL3_B 7 0 G odd C...

Страница 12: ...r CC3 is used to clear the memory FIFO or stop filling the memory circular buffer CC2 is used to read the top most images from memory FIFO or to read the oldest non read image from memory Circular buf...

Страница 13: ...large or small gain values can introduce significant artifacts in your images The gain table contains 8 bit values which are formatted unsigned 1 7 format that is one binary digit followed by 7 fract...

Страница 14: ...out the buffers faster than they are collected image collection will not stop For example you can program the camera to total 10 images in each buffer before passing it to the host The host triggers t...

Страница 15: ...rements of 15 nS In triggered modes the frame period is also affected by the exposure delay In multiple trigger mode the exposure delay only affects the time until the first readout of the trigger seq...

Страница 16: ...re trigger event occurs too soon to start the subsequent exposure after the programmed delay the next exposure will start as soon as possible thereafter This prevents the effect of running at submulti...

Страница 17: ...ate storage page of flash memory Comparators in the Control FPGA check for changes in the DAC settings and re load the DAC s whenever the values are changed This can happen as a result of the host com...

Страница 18: ...d to the Data FPGA 8 If the Pointer to the Data FPGA initialization area is valid and the length is valid and non zero the Data FPGA initialization is read from flash and forwarded to the Data FPGA 9...

Страница 19: ...11 Part Number ASCII 800 5 388 3 Part Revision ASCII 010 391 9 Serial Number ASCII XXX 400 128 FPGA bitstream file header from mkbin Null terminated string Table 3 Flash Memory Header Page 15 CAMERA S...

Страница 20: ...internal registers that implement the camera state change too Some of these are located in the Control FPGA and some in the Data FPGA The Control FPGA forwards state data to the Data FPGA whenever it...

Страница 21: ...rate can be changed with a command on the serial link or via the USB port To allow recovery after inadvertent setting of a higher baud rate than the host can handle the serial link will revert to 960...

Страница 22: ...on after errors Sending two carriage returns will always reset the serial link to its default state waiting for new command In addition when the serial logic detects a framing error or protocol error...

Страница 23: ...h size On error a response code is returned The first byte is the reason which may be 00 01 or 02 00 indicates bad header flash part type 01 indicates illegal starting page address 02 indicates load w...

Страница 24: ...M Read Flash This command takes arguments that form the precise command to send to the flash memory followed by the command length and data length to be read in bytes Command length includes any don t...

Страница 25: ...posures minimum exposure is limited by the serial baud rate To support this mode any characters between the O and the cr are ignored Thus the total command length in characters can be used to determin...

Страница 26: ...tion data does not start with 3C A5 0F 96 the Control FPGA will not send this command Serial Responses Normally the data sent to the Data FPGA from the Control FPGA is limited in bandwidth at the sour...

Страница 27: ...tion and flash data read but this is where the largest time is spent Using the algorithm from previous PicoBlaze designs Video Combiners and bit wiggling the best data rate for FPGA download would be...

Страница 28: ...e UART via register 0xFD The validity of the current data depends on the error bits listed below This and other receive status bits are cleared when the UART is read 6 Fget8 on write Transmitter Ready...

Страница 29: ...s enable signal is active Sensor Register Map All of the following registers can only be accessed when the sensor register write enable signal is set This is bit 2 of register 0xfb Writing these regis...

Страница 30: ...edge triggered modes When this bit is set the readout timing is synchronized to the exposure 3 Invert Camera Link CC1 Trigger Setting this bit to 1 indicates the CC1 trigger input on Camera Link is ac...

Страница 31: ...ut 19 DATA FPGA This specification contains an overview of the functionality and design details for the Data FPGA within the FastCamera 13 40 The Data FPGA accepts the video data from the Sensor and s...

Страница 32: ...32...

Страница 33: ...video data from the FIFO operates at the specified Camera link clock rate This rate can be selected to be 33 42 5 66 or 85Mhz The output state machine controls the reading of the FIFO and outputting...

Страница 34: ...for Control FPGA base system extension 128 384 Available for Data FPGA functionality extensions Table 4 Camera State Memory Layout Whenever the state memory is updated from host or flash the actual i...

Страница 35: ...7 0 4 n 0 CL1_B 7 4 CL1_C 7 0 4 n 1 CL2_C 3 0 CL2_B 7 0 4 n 2 CL2_C 7 4 CL2_A 7 0 4 n 3 Four Taps 12 bits Medium 0x0D CL1_B 7 0 CL1_A 7 0 4 n 0 CLA_A 7 0 CL1_C 7 0 4 n 1 CL2_C 7 0 CL2_B 7 0 4 n 2 CL3...

Страница 36: ...L Tx25 F1 Tx25 H8 Tx25 C4 Tx26 F2 Tx26 H9 Tx26 C5 Tx27 LVAL Tx27 LVAL Tx27 19 5 1 2 10 Tap 8 bit mode This mode Basler A501k mode uses all of the RX TX bits of the camera link interface so it needs to...

Страница 37: ...FC40 Camera Link Clock Frequency 0x00 33MHz 0x00 30MHz 0x01 42 5MHz 0x01 42 5MHz 0x02 66MHz 0x02 60MHz 0x03 85MHz 0x03 85MHz 19 5 3 Binning Control setting This byte controls which 16 bits are selecte...

Страница 38: ...OI 10pixels column Horiz_binning Vertical_binning So for example when running full resolution 1280 pixels per row no binning in 1Tap mode at 33Mhz clock rate the calculation is Time_required_over_Came...

Страница 39: ...Order of the pixels output at each clock cycle Pixels read during the current clock cycle to be available for on subsequent clock cycles 1 Tap 1 2 3 4 5 6 7 8 9 T 1 2 3 4 5 6 7 8 9 T whole FIFO prere...

Страница 40: ...6 7 8 9 10 The data from the FIFOs was shown here as a byte per pixel so signal FIFO_d12 15 0 represents pixel2 on bits 15 8 and pixel1 on bits 7 0 Signal FF_RDxx are the FIFO read signals Signal ff_...

Страница 41: ...y the state machine starts with a pre read of the whole FIFO during which pixels 1 Ten are read The state machine then continues in a 5 cycle loop until the end of the line is detected ff_lval deasser...

Страница 42: ...he state machine starts with a pre read of the whole FIFO during which pixels 1 Ten are read The state machine then continues in a 5 cycle loop until the end of the line is detected ff_lval deasserted...

Страница 43: ...tate machine starts with a pre read of the whole FIFO during which pixels 1 Ten are read The state machine then continues in a 5 cycle loop until the end of the line is detected ff_lval deasserted The...

Страница 44: ...44 20 7 Sensor Interface The FPGA interface to the sensor consists of the following signals mv_hsck4 2 1 0 mv_hsck0 mv_hsck1 mv_hsck2 mv_hsck4 mv_sel0 mv_sel1 mv_sel2 mv_sel4 mv_hsd mv_data...

Страница 45: ...rts USB 2 0 which provides up to about 40 MBytes sec transfer rates You will probably get less it depends on your computer typically the transfer rate is more than 30 Mbytes sec 22 CAMERA CONTROL PROG...

Страница 46: ...Library DLL Or ActiveX Control Operating System Provided USB Drivers FastVision Provided USB Device Driver FastVision FastViewer Software Library DLL Or ActiveX Control 23 4 Using a FastVision suppli...

Страница 47: ...dware connections are Camera Lens Your Computer Power Supply FastVision Provided Frame Grabber 1 or 2 Camera Link Cables 23 4 2 The software connections are Camera Serial And Channel Link Devices Driv...

Страница 48: ...ens A power supply for the camera One or more Camera Link cables Your third party framegrabber AIA compliant software for your framegrabber FastVision supplied camera control program 23 5 1 The hardwa...

Страница 49: ...ber Your Software Camera Link Standard DLL FastVision Camera Control Application This will only work if your framegrabber supports the Camera Link standard serial interface protocol and your framegrab...

Страница 50: ...tacting Technical Support To speak with a Technical Support Representative on the telephone call the number below and ask for Technical Support Telephone 603 891 4317 If you would rather FAX a written...

Страница 51: ...up in the fields that were not encountered during our testing at FastVision If you encounter a software or hardware problem or anomaly please contact us immediately for assistance If a fix is not avai...

Страница 52: ...f the person we should contact if we have questions FastVision LLC 131 Daniel Webster Highway 529 Nashua NH 03060 USA Telephone 603 891 4317 FAX 603 891 1881 Web site http www fast vision com Electron...

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