Delta Tau Geo MACRO, Руководство пользователя и справочное руководство

Страница: 168 / 205

Geo MACRO Drive User Manual
156 Geo Macro Drive MI-Variable Reference
DAC_CLK Frequency = 39.3216 MHz / (2 ^ 3) = 4.9152 MHz
ADC_CLK Frequency = 39.3216 MHz / (2 ^ 4) = 2.4576 MHz
MI993 controls the frequency of three hardware clock frequencies -- SCLK, PFM_CLK, DAC_CLK and
ADC_CLK -- for the handwheel interface channels 1 and 2. It is a 12-bit variable consisting of four
independent 3-bit controls, one for each of the clocks. Each of these clock frequencies can be divided
down from a starting 39.3216 MHz frequency by powers of 2, 2
N , from 1 to 128 times (N=0 to 7). This
means that the possible frequency settings for each of these clocks are:
Frequency Divide by Divider N in
1/2N
39.3216 MHz 1 0
19.6608 MHz 2 1
9.8304 MHz 4 2
4.9152 MHz 8 3
2.4576 MHz 16 4
1.2288 MHz 32 5
611.44 kHz 64 6
305.72 kHz 128 7
Very few Geo MACRO Station users will be required to change the setting of MI993 from the default
value.
The encoder sample clock signal SCLK controls how often 2-axis board’s digital hardware looks at the
encoder inputs. PMAC2 can take at most one count per SCLK cycle, so the SCLK frequency is the
absolute maximum encoder count frequency. SCLK also controls the signal propagation through the
digital delay filters for the encoders and flags; the lower the SCLK frequency, the greater the noise pulse
that can be filtered out. The SCLK frequency should optimally be set to the lowest value that can accept
encoder counts at the maximum possible rate.
The pulse-frequency-modulation clock PFM_CLK controls the PFM circuitry on the 2-axis board that can
create pulse and direction outputs. The maximum pulse frequency possible is 1/4 of the PFM_CLK
frequency. The PFM_CLK frequency should optimally be set to the lowest value that can generate pulses
at the maximum frequency required.
The ADC_CLK controls the serial data frequency from A/D converters, either for digital current loop
closure, or from the A/D converter options.
The DAC-CLK controls the serial data frequency to D/A converters which are optional. To determine the
clock frequencies set by a given value of MI993, use the following procedure:
1. Divide MI993 by 512 and round down to the nearest integer. This value N1 is the ADC_CLK
divider.
2. Multiply N1 by 512 and subtract the product from MI993 to get MI993'. Divide MI993' by 64 and
round down to the nearest integer. This value N2 is the DAC_CLK divider (not relevant here).
3. Multiply N2 by 64 and subtract the product from MI993' to get MI993''. Divide MI993'' by 8 and
round down to the nearest integer. This value N3 is the PFM_CLK divider.
4. Multiply N3 by 8 and subtract the product from MI993''. The resulting value N4 is the SCLK divider.
Examples:
The maximum encoder count frequency in the application is 800 kHz, so the 1.2288 MHz SCLK
frequency is chosen. A pulse train up to 500 kHz needs to be generated, so the 2.4576 MHz PFM_CLK
frequency is chosen. ADCs and DACs are not used, so the default DAC_CLK frequency of 4.9152 MHz
and the default ADC_CLK frequency of 2.4576 MHz are chosen. From the table: