Delta Tau Geo MACRO, Руководство пользователя и справочное руководство

Страница: 167 / 205

Geo MACRO Drive User and Reference Manual
Geo Macro Drive MI-Variable Reference 155
Global & 2-Axis Board I-Variables
MI-Variables numbered in the MI990s control hardware aspects of the “DSPGATE2” ASIC. This IC
controls operation of the Geo MACRO Ring on all Geo MACRO Stations. This IC also controls the
frequency of the clock signals for the 2-axis piggyback board (machine interface channels 1 & 2).
MS{node},MI992 MaxPhase Frequency Control
Range: 0 - 32767
Units: MaxPhase Frequency = 117,964.8 kHz / [2*MI992+3]
PWM Frequency = 117,964.8 kHz / [4*MI992+6]
Default: 6527
MaxPhase Frequency = 117,964.8 / 13057 = 9.0346 kHz
PWM Frequency = 117,964.8 / 26114 = 4.5173 kHz
MI992 controls the "maximum phase" clock frequency for the Geo MACRO Station, and the PWM
frequency for supplementary handwheel interface channels 1 and 2. It does this by setting the limits of
the PWM up-down counter, which increments and decrements at the PWMCLK frequency of 117,964.8
kHz (117.9648 MHz).
The actual phase clock frequency is divided down from the maximum phase clock according to the setting
of MI997. The phase clock frequency must be the same as the ring update frequency as set by the ring
controller - usually a Turbo PMAC2. If the ring controller is a PMAC2 Ultralite, MI992 and MI997 on
the 16-Axis MACRO Station should be set to the same values as MI992 and MI997 on the PMAC2
Ultralite.
To set MI992 for a desired "maximum phase" clock frequency, the following formula can be used:
MI992 = (117,964.8 kHz / [2*MaxPhase (kHz)]) - 1 (rounded down)
Examples:
To set a PWM frequency of 10 kHz and therefore a MaxPhase clock frequency of 20 kHz:
MI992 = (117,964.8 kHz / [4*10 kHz]) - 1 = 2948
To set a PWM frequency of 7.5 kHz and therefore a MaxPhase clock frequency of 15 kHz:
MI992 = (117,964.8 kHz / [4*7.5 kHz]) - 1 = 3931
MS{node},MI993 Hardware Clock Control Handwheel Channels
Range: 0 - 4095
Units: MI993 = Encoder SCLK Divider
+ 8 * PFM_CLK Divider
+ 64 * DAC_CLK Divider
+ 512 * ADC_CLK Divider
where:
Encoder SCLK Frequency = 39.3216 MHz / (2 ^ Encoder SCLK Divider)
PFM_CLK Frequency = 39.3216 MHz / (2 ^ PFM_CLK Divider)
DAC_CLK Frequency = 39.3216 MHz / (2 ^ DAC_CLK Divider)
ADC_CLK Frequency = 39.3216 MHz / (2 ^ ADC_CLK Divider)
Default: 2258 = 2 + (8 * 2) + (64 * 3) + (512 * 4)
Encoder SCLK Frequency = 39.3216 MHz / (2 ^ 2) = 9.8304 MHz
PFM_CLK Frequency = 39.3216 MHz / (2 ^ 2) = 9.8304 MHz