Datascope Passport 2, Руководство по обслуживанию

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Passport 2®/Passport 2 LT™ Service Manual 0070-10-0441 2 - 53
Theory of Operation Passport 2 NIBP Module (P/N 0670-00-0730 or 0670-00-0746-01)
The EEPROM will be programmed using a PC based program script to download hardware
and software revision history.
The HC16Z1 software can detect bad sector data in the serial EEPROM using checksums
which can be verified during initialization.
2.15.16 Hardware Locks
The EEPROM are hardware write protected by installing jumper J3 (JMODE* signal line).
Removing J3 will automatically remove the hardware write protection feature allowing the
device to be written while in one of the auxiliary modes.
2.15.17 Reset
Low Power Reset, U8
A Dallas Semiconductor DS1811 device monitors the PCB’s VCC voltage and activates RST*
before it falls below 4.5V. Since the HC16Z1 timing characteristics are specified with VCC
at 5V+/-10%, a valid VCC voltage is guaranteed while the device is out of reset. The flash is
also reset by RST*, which prevents spurious flash writes during power cycling.
2.15.18 Host Reset
The MODRESET* signal from J1 allows the host to reset the main processor (HC16Z1) on the
PCB. A NOR gate (U14) inverts the signal and the Q7 FET pulls RST* low when
MODRESET* is activated.
RST* is pulled up by R17. This resistor’s value was chosen in order to meet the RST* timing
requirements of the HC16Z1. If the RST* rise time is too slow, the HC16Z1 will assume there
is an external reset and repeatedly drive RST* low itself. This rise time is governed by the
capacitive loads on RST* as well.
Note, RST* is not connected to the AT90S4433 reset (PROGRAM*) in order to prevent an
HC16Z1 reset from bringing the PCB out of the emergency shutdown state.