Datascope Passport 2, Руководство по обслуживанию

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CPU Control Module Theory of Operation
2 - 6 0070-10-0441 Passport 2®/Passport 2 LT™ Service Manual
The digital outputs LRCLK and SOUT from the U12 provide the clock and the digital audio
data input to the stereo D/A converter. This is a complete stereo digital to analog system
including digital interpolation, 128X third order delta-sigma D/A conversion, digital de-
emphasis and analog filtering. The de-emphasis circuit is not used in this application.
The stereo outputs from the U27 are summed together and is fed to the power amplifier U13,
which is a bridge connected audio power amplifier capable of delivering 1watt of
continuous average power to an 8 ohm speaker load. The circuit is optimized for a
frequency range of 100Hz to 10KHz.
2.1.11 Module ID, U44
There is a Module ID port implemented by U44 that is used to read the ID code from any
device that is connected to Docking connector, J9. These devices can be either a Base Station
or Comm Ports. Each of these devices has a unique code. The base station is hot swappable,
while the Comm Ports are not hot swappable. When any base station is connected or
removed from the Docking connector J9 using live insertion, an interrupt IRQ4* is generated.
When a Comm Port, which is not hot swappable, is powered up with a
Passport 2
monitor, the module ID is read by software, and is in the flow of the start-up code. This
reading of the module ID upon power up is automatic and is not dependent on whether there
is an IRQ4* or not, or if a base station or Comm Port is connected. Therefore a duplicate
IRQ4*, which may be generated by the modules upon power up, is redundant.
This IRQ4* interrupt is falling edge triggered and can be sourced only when IRQB* is
previously low and IRQA* then follows and goes low. The state diagram for the IRQA* /
IRQB* logic is such that IRQB* must be low prior to an IRQA* falling edge. In the Comm
Ports, IRQB* is tied to GND and IRQA* is driven low after the circuitry becomes active, thus
the condition is met. In the base station, IRQB* is driven low whenever there is power
applied to the base station, and IRQA* is driven low whenever the base station is powered
AND the monitor's 3.3V power is within regulation, again, meeting the condition.
IRQA* and IRQB* (on J9-17, J9-67) are both generated external to the CPU board.
Components involved in the state control logic on the CPU board, affecting the rise time of
IRQA* and IRQB*, are components R185, R174, C427, and D9. U64 is used to generate
IRQ4*.
The signal that enables U44 to drive the Module ID field onto the data bus is MODIDCS*,
active low. It is generated by a sub-circuit of CPLD U1 by decoding Address lines A[18:20]
in conjunction with an active CS3*.