Datascope Passport 2, Руководство по обслуживанию

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NEC 10.4” Display/Keypad Interface Board Theory of Operation
2 - 44 0070-10-0441 Passport 2®/Passport 2 LT™ Service Manual
Operation of both timers begins with both RESET lines held high. The first timer circuit
operates in an astable mode. The output of the first timer circuit is approximately 1.5ms with
a 67% duty cycle. The period and the duty cycle are determined by R58, R56 and C11. The
output of the first timer circuit is fed into the trigger input of the second timer circuit. The
second timer circuit begins it’s operation on the falling edge of the input signal. The duty
cycle is determined by the value of R59, R61 and C12. The amplitude of the output is
approximately 1.55 volts less than the power supply.
To obtain a 100% duty cycle, J8 is unjumpered. This disconnects the output of the monostable
circuit from U9 and ties the input of U9 to the voltage across R63, which is setup by the
voltage divider of R60, R62 and R63. In this configuration J6 and J7 are unjumpered. To
obtain a 50% duty cycle, J6 and J8 are jumpered, J7 is unjumpered. The combination of R59
and C12 produces the 50% duty cycle. To obtain a 75% duty cycle, J7 and J8 are jumpered
and J6 is unjumpered. The combination of R61 and C12 produces a 75% duty cycle.
The output of the monostable timer is used to drive a buffer with a 3 state output which is
controlled by VIDPWR*. In order to satisfy the input requirements of the buffer, U9, the output
of the monostable timer is stepped down by R62 and R63 for 50% and 75% duty cycles. For
the 100% duty cycle, the monostable timer is disabled and the input to U9 is stepped down
by R60, R62, R63 and +12V2. When VIDPWR* is low, U9 is turned on, providing the gate
voltage to Q1. Q1 turns on essentially shorting the gate on Q2 to ground. This turns on Q2,
providing current to flow to the control pin of the inverter, VCONT. R34 and C66 were
chosen to keep the Passport 2 CPU clock frequency (45 MHz) from contaminating the
VCONT signal and to permit a return to +12V_RET for the inverter frequency (41 KHz). R34
also provides a ground loop between 3VGND (VIDPWR*) and +12V_RET (VCONT). When
VIDPWR* is high, there is no output on U9.
R64 and C65 sustain the supply voltage for U9 as the input on U9 changes from high to low
and low to high.
CR1 provides ESD protection for the circuit from transients from the inverter.
2.14.3 Speaker Interface
The system speaker is connected to J2. The NEC 10.4” Display/Keypad Interface Board
functions as a pass through for audio signals.
2.14.4 Encoder Interface
The optical encoder for the keypad is connected to J4. Phase signals (CHA/CHB) and the
switch contact signal (SW) are passed through the NEC 10.4” Display/Keypad Interface
Board to an ADC on the CPU board.