xStack
®
DGS-3400 Series Layer 2 Gigabit Managed Switch CLI Manual
223
D G S – 3 4 2 6 : 5 # s h o w a c c e s s _ p r o f i l e
C o m m a n d : s h o w a c c e s s _ p r o f i l e
A c c e s s P r o f i l e T a b l e
A c c e s s P r o f i l e I D : 1 T Y P E : E t h e r n e t
= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
M A S K O p t i o n :
V L A N 8 0 2 . 1 p
– – – – – – – – – – – – – – – – –
A c c e s s I D : 3 M o d e : P e r m i t ( r e p l a c e d ) p r i o r i t y : 1 R X R a t e ( 6 4 K b p s ) :
n o _ l i m i t
P o r t s : 1 : 1
– – – – – – – – – – – – – – – – –
T r i n i t y 1
= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
A c c e s s P r o f i l e I D : 2 T Y P E : I P
= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
M A S K O p t i o n :
P r o t o c o l I D
– – – – – – – – – – – – – – – – – – – –
A c c e s s I D : 2 M o d e : D e n y
P o r t s : 1 : 2
– – – – – – – – – – – – – – – – – – – –
2
= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
A c c e s s P r o f i l e I D : 3 T Y P E : P a c k e t C o n t e n t
= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
M A S K O p t i o n :
O f f s e t 0 – 1 5 : 0 x F F F F F F F F 0 x F F F F F F F F 0 x F F F F F F F F 0 x F F F F F F F F
O f f s e t 1 6 – 3 1 : 0 x 0 0 0 0 F F F F 0 x F F F F 0 0 0 0 0 x 0 0 0 0 0 0 0 F 0 x 0 F 0 0 0 0 0 0
A c c e s s I D : 1 M o d e : D e n y
P o r t s : 1 : 1
O f f s e t 0 – 1 5 : 0 x 1 1 1 1 1 1 1 1 0 x 1 1 1 1 1 1 1 1 0 x 1 1 1 1 1 1 1 1 0 x 1 1 1 1 1 1 1 1
O f f s e t 1 6 – 3 1 : 0 x 0 0 0 0 1 1 1 1 0 x 1 1 1 1 0 0 0 0 0 x 0 0 0 0 0 0 0 1 0 x 0 1 0 0 0 0 0 0
= = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
T o t a l E n t r i e s : 3
D G S – 3 4 2 6 : 5 #
create cpu access_profile
Purpose
Used to create an access profile specifically for
CPU Interface Filtering
on the Switch
and to define which parts of each incoming frame’s header the Switch will examine.
Masks can be entered that will be combined with the values the Switch finds in the
specified frame header fields. Specific values for the rules are entered using the
config
cpu access_profile
command, below.
Syntax
create cpu access_profile [ethernet {vlan | source_mac <macaddr 000000000000–
ffffffffffff> | destination_mac <macaddr 000000000000–ffffffffffff> | ethernet_type}
(1) | ip {vlan | source_ip_mask <netmask> | destination_ip_mask <netmask> | dscp
| [icmp {type | code} | igmp {type} | tcp {src_port_mask <hex 0x0–0xffff> |
dst_port_mask <hex 0x0–0xffff> | flag_mask [all | {urg | ack | psh | rst | syn | fin}
(1) ]} | udp {src_port_mask <hex 0x0–0xffff> | dst_port_mask <hex 0x0–0xffff>} |
protocol_id_mask {<hex 0x0–0xff> {user_define_mask <hex 0x0–0xffffffff>}]} (1) |
packet_content_mask {offset 0–15 <hex 0x0–0xffffffff> <hex 0x0–0xffffffff> <hex
0x0–0xffffffff> <hex 0x0–0xffffffff>| offset 16–31 <hex 0x0–0xffffffff> <hex 0x0–
0xffffffff> <hex 0x0–0xffffffff> <hex 0x0–0xffffffff> | offset 32–47 <hex 0x0–0xffffffff>
<hex 0x0–0xffffffff> <hex 0x0–0xffffffff> <hex 0x0–0xffffffff> | offset 48–63 <hex
