Broadcom BCM5706C, Руководство пользователя

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User Guide NetXtreme II
January 2010
Bro a d c o m Co rp o r a ti o n
Document ENGSRVT52-CDUM100-R Diagnostic Test Descriptions Page 233
C1 CPU Logic and DMA
Interface Verifies the basic logic functionality of all the on-chip CPUs. It also exercises the
DMA interface exposed to those CPUs. The internal CPU tries to initiate DMA
activities (both read and write) to system memory and then compares the values
to confirm that the DMA operation completed successfully.
C2 RBUF Allocation Verifies the RX buffer (RBUF) allocation interface by allocating and releasing
buffers and checking that the RBUF block maintains an accurate count of the
allocated and free buffers.
C3 CAM Access Verifies the content-addressable memory (CAM) block by performing read,
write, add, modify, and cache hit tests on the CAM associative memory.
C4 TPAT Cracker Verifies the packet cracking logic block (i.e., the ability to parse TCP, IP, and
UDP headers within an Ethernet frame) as well as the checksum/CRC offload
logic. In this test, packets are submitted to the chip as if they were received over
Ethernet and the TPAT block cracks the frame (identifying the TCP, IP, and UDP
header data structures) and calculates the checksum/CRC. The TPAT block
results are compared with the values expected by Broadcom NetXtreme II User
Diagnostics and any errors are displayed.
C5 FIO Register The Fast IO (FIO) verifies the register interface that is exposed to the internal
CPUs.
C6 NVM Access and
Reset-Corruption Verifies non-volatile memory (NVM) accesses (both read and write) initiated by
one of the internal CPUs. It tests for appropriate access arbitration among
multiple entities (CPUs). It also checks for possible NVM corruption by issuing a
chip reset while the NVM block is servicing data.
C7 Core-Reset Integrity Verifies that the chip performs its reset operation correctly by resetting the chip
multiple times, checking that the bootcode and the internal uxdiag driver loads/
unloads correctly.
C8 DMA Engine Verifies the functionality of the DMA engine block by performing numerous DMA
read and write operations to various system and internal memory locations (and
byte boundaries) with varying lengths (from 1 byte to over 4 KB, crossing the
physical page boundary) and different data patterns (incremental, fixed, and
random). CRC checks are performed to ensure data integrity. The DMA write
test also verifies that DMA writes do not corrupt the neighboring host memory.
C9 VPD Exercises the Vital Product Data (VPD) interface using PCI configuration cycles
and requires a proper bootcode to be programmed into the non-volatile memory.
If no VPD data is present (i.e., the VPD NVM area is all 0s), the test first initializes
the VPD data area with non-zero data before starting the test and restores the
original data after the test completes.
C11 FIO Events Verifies that the event bits in the CPU’s Fast IO (FIO) interface are triggering
correctly when a particular chip events occur, such as a VPD request initiated by
the host, an expansion ROM request initiated by the host, a timer event
generated internally, toggling any GPIO bits, or accessing NVM.
Group D: Ethernet Traffic Tests
D1 MAC Loopback Enables MAC loopback mode in the adapter and transmits 5000 Layer 2 packets
of various sizes. As the packets are received back by Broadcom NetXtreme II
User Diagnostics, they are checked for errors. Packets are returned through the
MAC receive path and never reach the PHY. The adapter should not be
connected to a network.
D2 PHY Loopback Enables PHY loopback mode in the adapter and transmits 5000 Layer 2 packets
of various sizes. As the packets are received back by Broadcom NetXtreme II
User Diagnostics, they are checked for errors. Packets are returned through the
PHY receive path and never reach the wire. The adapter should not be
connected to a network.
Table 3: Diagnostic Tests (Cont.)
Test
Description
Number Name