Beckhoff EL1502, Документация

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Commissioning
EL1502, EL1512 118 Version: 3.5
• DC-synchronous
In DC operating mode determination of the counter value is triggered cyclically at constant intervals
through the integrated DC unit, synchronous with the bus cycle as standard. More uniform polling
offers higher-quality position data for a higher-level control algorithm, for example. In the EL1502 the
SYNC0 signal acts as trigger.
Fig. 144: “DC” tab (Distributed Clocks)
When DC Synchronous operating mode is activated TwinCAT selects settings that ensure reliable operation
of the EL1502 with current position data. This means that determination of the current counter value is
triggered by the SYNC0 signal at highly constant intervals and in good time (i.e. with an adequate safety
buffer) before retrieving EtherCAT datagram is started.
If necessary, the SYNC0 signal can be shifted along the time axis to the right/later or left/earlier in associated
dialogs by specifying a “User defined Shift Time”, see Fig.
Advanced Distributed Clock (DC) settings,
EL1502 terminal.
• A right-shift (positive shift value) will delay the counter value query, which means the position value
becomes more current from the PLC perspective. However, this increases the risk that the position
determination may not be finished in time before the arrival of EtherCAT frame, so that no current
position value is available in this cycle.
• A left-shift (negative shift value) means the counter value will be queried earlier, resulting in older
position values, with an associated increase in the safety buffer before the arrival of the EtherCAT
datagram. This setting may be useful in systems with high real-time jitter, if no Industrial PCs from
Beckhoff are used for control purposes, for example.
CAUTION
CAUTION! Risk of device damage!
The mentioned notes and information should be used advisedly. The EtherCAT master automatically allo-
cates SYNC0 and SYNC1 settings that support reliable and timely process data acquisition.
User intervention at this point may lead to undesired behavior.
If these settings are changed in the System Manager, no plausibility checks are carried out on the software
side.
Correct function of the terminal with all conceivable setting options cannot be guaranteed.
Default setting
The cyclic read of the inputs is triggered by the SYNC0 pulse (interrupt) from the DC in the EL1502. The
EtherCAT master sets the Sync Unit Cycle time value to the PLC cycle time and therefore the EtherCAT
cycle time as standard. See Fig.
Advanced Distributed Clock (DC) settings, EL1502 terminal: 4000µs = 4 ms,
as TwinCAT is in configuration mode.