AT32F425
Series Reference Manual
2022.03.30
Page 50
Ver 2.01
divider must remain between 2 MHz and 16 MHz, and the VCO operating frequency must be kept
between 500 MHz and 1000 MHz. The PLL must be configured before enabling it. The reason is that
the configuration parameters cannot be changed once PLL is enabled. The PLL clock signal is not
released before it becomes stable.
PLL formula:
PLL output clock = PLL input clock x PLL frequency multiplication factor / (PLL pre-divider factor x PLL
post-divider factor)
500MHz <= PLL input clock x PLL frequency multiplication factor / PLL pre-divider factor <= 1000MHz
2MHz <= PLL input clock / PLL pre-divider factor <= 16MHz
For example, when the PLL input clock is 25 MHz, the PLL output frequency equals 25 x 192 / (5 x 4) =
240 MHz
Low speed external oscillator (LEXT)
The LEXT oscillator provides two clock sources: LEXT crystal/ceramic resonator and LEXT bypass.
LEXT crystal/ceramic resonator:
The LEXT crystal/ceramic resonator provides a 32.768 KHz low-speed clock source. The LEXT clock
signal is not released before it becomes stable.
LEXT bypass clock
In this mode, an external clock source with a frequency of 32.768 kHzcan be provided. The external
clock signal should be connected to the LEXT_IN pin while the LEXT_OUT can be released for GPI
control.
Low speed internal RC oscillator (LICK)
The LICK oscillator is clocked by an internal low-speed RC oscillator. The clock frequency is between
30 kHz and 60 kHz. It acts as a low-power clock source that can be kept running in Deepsleep mode
and Standby mode for watchdog and auto-wakeup unit.
The LICK clock signal is not released before it becomes stable.
4.1.2
System clock
After a system reset, the HICK oscillator is selected as system clock. The system clock can make flexible
switch among HICK oscillator, HEXT oscillator and PLL clock. However, a switch from one clock source
to another occurs only if the target clock source becomes stable. When the HICK oscillator is used
directly or indirectly through the PLL as the system clock, it cannot be stopped.
4.1.3
Peripheral clock
Most peripherals use HCLK, PCLK1 or PCLK2 clock. The individual peripherals have their dedicated
clocks.
System Tick timer (SysTick) is clocked by HCLK or HCLK/8.
ADC is clocked by APB2 divided by 2, 4, 6, 8, 12.
The timers are clocked by APB1/2. In particular, if the APB prescaler is 1, the timer clock frequency is
equal to that of APB1/2; otherwise, the timer clock frequency doubles that of the APB1/2 frequency.
The USB clock source can be switched between HICK and PLL frequency divider. If the HICK is selected
as a clock source, the USB clock should be set as 48 MHz; If the PLL frequency divider is selected as a
clock source, the USB frequency divider provides 48 MHz USBCLK, and thus the PLL must be set as
48*N*0.5 MHz (N=2,3,4,5…)
ERTC clock sources: divided HEXT oscillator, LEXT oscillator and LICK oscillator. Once the clock source
is selected, it cannot be altered without resetting the battery powered domain. If the LEXT is used as an
ERTC clock, the ERTC is not affected when the VDD is powered off. If the HEXT or LICK is selected as
an ERTC clock, the ERTC state is not guaranteed when both HEXT and LICK are powered off.
Watchdog is clocked by LICK oscillator. If the watchdog is enabled by either hardware option or software
access, the LICK oscillator is forced ON. The clock is provided to the watchdog only after the LICK
oscillator temporization.
