Bus Interface Unit and Write Buffer
Copyright © ARM Limited 2000. All rights reserved.
6-13
NCB
Data reads and writes are not cached. Writes are buffered, and so
cannot be externally aborted. Reads can be externally aborted.
Reads cause the write buffer to drain.
If the DCache hits for this type of access, there has been a
programming error. DCache hits are ignored and the DCache line
is not updated for a read.
Swap instructions operation on data in an NCB region are made to
perform NCNB type accesses and are not buffered.
WT
Searches the DCache for reads and writes. Reads that miss in the
DCache cause a line fill. Reads that hit in the DCache do not
perform an external access. All writes are buffered, regardless of
whether they hit or miss in the DCache. Writes that hit in the
DCache update the cache but do not mark the cache line as dirty,
because the write is also sent to the write buffer. Writes cannot be
externally aborted. DCache linefills cause the write buffer to drain
before the linefill starts.
WB
Searches the DCache for reads and writes. Reads that miss in the
DCache cause a line fill. Reads that hit in the DCache do not
perform an external access. Writes that miss in the DCache are
buffered. Writes that hit in the DCache update the cache line,
mark it as dirty, and do not send the data to the write buffer.
DCache write-backs are buffered. Writes (write-miss and
write-back) cannot be externally aborted. DCache linefills cause
the write buffer to drain before the linefill starts.
6.5.2
Enabling and disabling the write buffer
You cannot directly enable or disable the write buffer. However, you can prevent the
write buffer being used by setting the properties of a memory region to be NCNB, or by
disabling the protection unit.
6.5.3
Self-modifying code
Instruction fetches and NCNB reads bypass the write buffer. If you write
self-modifying code to a bufferable or cachable region, then it is essential that you drain
the write buffer before fetching instructions from these addresses.
Содержание ARM946E-S
Страница 1: ...ARM DDI 0155A ARM946E S Technical Reference Manual ...
Страница 6: ...vi Copyright ARM Limited 2000 All rights reserved ARM DDI 0155A 04 Limited Confidential ...
Страница 54: ...Programmer s Model 2 34 Copyright ARM Limited 2000 All rights reserved ARM DDI 0155A ...
Страница 70: ...Caches 3 16 Copyright ARM Limited 2000 All rights reserved ARM DDI 0155A ...
Страница 78: ...Protection Unit 4 8 Copyright ARM Limited 2000 All rights reserved ARM DDI 0155A ...
Страница 98: ...Bus Interface Unit and Write Buffer 6 14 Copyright ARM Limited 2000 All rights reserved ARM DDI 0155A ...
Страница 112: ...Coprocessor Interface 7 14 Copyright ARM Limited 2000 All rights reserved ARM DDI 0155A ...