Bus Interface Unit and Write Buffer
Copyright © ARM Limited 2000. All rights reserved.
6-3
6.2
AHB bus master interface
The ARM946E-S implements a fully compliant AHB bus master interface as defined in
the AMBA Rev 2.0 Specification. See this document for a detailed description of the
AHB protocol.
6.2.1
About the AHB
The AHB architecture is based on separate cycles for address and data (rather than
separate clock phases, as in ASB). The address and control for an access are broadcast
from the rising edge of HCLK in the cycle before the data is expected to be read or
written. During this data cycle, the address and control for the next transfer are driven
out. This leads to a fully pipelined address architecture.
When an access is in its data cycle, a slave can extend an access by driving the
HREADY signal LOW. This stretches the current data cycle, and therefore the
pipelined address and control for the next transfer is also stretched. This provides a
system where all AHB masters and slaves sample HREADY on the rising edge of
HCLK to determine whether an access has completed and a new address can be
sampled or driven out.
6.2.2
ARM946E-S transfer descriptions
The ARM946E-S only generates three of the possible transfer types defined in the
AMBA Specification. These are:
IDLE
HTRANS[1:0] = 00
NONSEQ
HTRANS[1:0] = 10
SEQ
HTRANS[1:0] = 11
The BUSY encoding (HTRANS[1:0] = 01) is not used by the ARM946E-S.
Содержание ARM946E-S
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