ARM ARM946E-S, Техническое справочное руководство

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AC Parameters
ARM DDI 0155A Copyright © ARM Limited 2000. All rights reserved. A-9
A.2 AC timing parameter definitions
Table A-1 shows target AC parameters. All figures are expressed as percentages of the
CLK period at maximum operating frequency.
Note
The figures quoted are relative to the rising clock edge after the clock skew for internal
buffering has been added. Inputs given a 0% hold figure therefore require a positive
hold relative to the top-level clock input. The amount of hold required is equivalent to
the internal clock skew.
Table A-1 Timing parameter definitions
Symbol Parameter Min Max
T
cyc
CLK cycle time 100% -
T
ishen
HCLKEN input setup to rising CLK 85% -
T
ihhen
HCLKEN input hold from rising CLK - 0%
T
isrst
HRESETn de-assertion input setup to rising CLK 90% -
T
ihrst
HRESETn de-assertion input hold from rising CLK - 0%
T
ovreq
Rising CLK to HBUSREQ valid - 30%
T
ohreq
HBUSREQ hold time from rising CLK >0% -
T
ovlck
Rising CLK to HLOCK valid - 30%
T
ohlck
HLOCK hold time from rising CLK >0% -
T
isgnt
HGRANT input setup to rising CLK 40% -
T
ihgnt
HGRANT input hold from rising CLK - 0%
T
ovtr
Rising CLK to HTRANS[1:0] valid - 30%
T
ohtr
HTRANS[1:0] hold time from rising CLK >0% -
T
ova
Rising CLK to HADDR[31:0] valid - 30%
T
oha
HADDR[31:0] hold time from rising CLK >0% -
T
ovctl
Rising CLK to AHB control signals valid - 30%
T
ohctl
AHB control signals hold time from rising CLK >0% -