Debug Support
8-8
Copyright © ARM Limited 2000. All rights reserved.
8.3.1
Reset
The JTAG interface includes a state-machine controller (the TAP controller). To force
the TAP controller into the correct state after power-up of the device you must apply a
reset pulse to the DBGnTRST signal, or you must cycle the JTAG state machine
through the TEST-LOGIC-RESET state. Before you can use the JTAG interface, you
must drive DBGnTRST LOW, and then HIGH again. If you do not intend using the
boundary scan interface, you can tie the DBGnTRST input permanently LOW.
Note
A clock on TCK is not necessary to reset the device.
The action of reset is as follows:
1.
Forces exit from debug state. The boundary scan chain cells do not intercept any
of the signals passing between the external system and the core.
2.
The IDCODE instruction is selected. If the TAP controller is put into the
SHIFT-DR state and TCK is pulsed, the contents of the ID register are clocked
out of TDO.
8.3.2
Pull-up resistors
The IEEE 1149.1 standard effectively requires TDI and TMS to have internal pull-up
resistors. In order to minimize static current draw, these resistors are not fitted to the
ARM9E-S core. Accordingly, the four inputs to the test interface (the TDO, TDI, and
TMS signals plus TCK) must all be driven to valid logic levels to achieve normal
circuit operation.
8.3.3
Instruction register
The instruction register is four bits in length. There is no parity bit. The fixed value
loaded into the instruction register during the CAPTURE-IR controller state is 0001.
Содержание ARM946E-S
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