Debug in Depth
B-60
Copyright © 2001, 2004 ARM Limited. All rights reserved.
ARM DDI 0210C
B.20
Programming restriction
Because the monitor mode enable bit does not put the ARM7TDMI into debug state, it
is necessary to change the contents of the watchpoint registers while external memory
accesses are taking place, rather changing them when in debug state (where the core is
halted).
If there is a possibility of false matches occurring during changes to the watchpoint
registers (caused by old data in some registers and new data in others) you must:
1.
Disable the watchpoint unit by setting EmbeddedICE-RT disable, bit [5] in the
debug control register.
2.
Poll the debug control register until the EmbeddedICE-RT disable bit is read back
as set.
3.
Change the other registers.
4.
Re-enable the watchpoint unit by clearing the EmbeddedICE-RT disable bit in the
debug control register.
See
The debug control register
on page B-51 for more information about controlling
core behavior at breakpoints and watchpoints.
Содержание ARM7TDMI
Страница 6: ...Contents vi Copyright 2001 2004 ARM Limited All rights reserved ARM DDI 0210C ...
Страница 10: ...List of Tables x Copyright 2001 2004 ARM Limited All rights reserved ARM DDI 0210C ...
Страница 14: ...List of Figures xiv Copyright 2001 2004 ARM Limited All rights reserved ARM DDI 0210C ...
Страница 46: ...Introduction 1 26 Copyright 2001 2004 ARM Limited All rights reserved ARM DDI 0210C ...
Страница 120: ...Coprocessor Interface 4 18 Copyright 2001 2004 ARM Limited All rights reserved ARM DDI 0210C ...
Страница 142: ...Debug Interface 5 22 Copyright 2001 2004 ARM Limited All rights reserved ARM DDI 0210C ...
Страница 276: ...Differences Between Rev 3a and Rev 4 C 6 Copyright 2001 2004 ARM Limited All rights reserved ARM DDI 0210C ...
Страница 282: ...Glossary Glossary 6 Copyright 2001 2004 ARM Limited All rights reserved ARM DDI 0210C ...