Chapter 5. Counter/Timers
42
Counter/Timer Operating Modes
Mode
Counter/Timer Output Operation
0
Transitions after programmed count expires. Gate
tied high to enable counting.
1
Transitions after programmed count expires. Gate
tied high to enable counting.
2
Periodic single pulse after programmed count
expires. Gate tied high to enable counting
3
Square wave with frequency equal to programmed
count. Gate tied high to enable counting.
4
Single pulse after programmed count expires. Gate
tied high to enable counting.
5
Single pulse after programmed count expires. Gate
tied high to enable counting.
PROGRAMMABLE REGISTERS
The counter/timers are accessed through four I/O addresses, as shown in the "Counter/Timer
Register Addressing" table below. Each counter/timer occupies an I/O port address through which
the preset count values are written and both the count and status information is read. The Control
register occupies the remaining I/O port address, which services all three counter/timers.
Counter/Timer Register Addressing
Address
Register
Operation
0040h
Channel 0 Count
Read/Write
0040h
Channel 0 Status
Read
0041h
Channel 1 Count
Read/Write
0041h
Channel 1 Status
Read
0042h
Channel 2 Count
Read/Write
0042h
Channel 2 Status
Read
0043h
Control
Write
Count Registers and Count Latch
Each counter/timer has a 16-bit Count Register and 16-bit Count Latch Register. The Count Register
is programmed with the initial count and is updated according to the mode in which the counter/timer
is programmed. The Count Latch Register is used to read the current count. The Access bits in the
General Control Register define the method for accessing the 16-bit Count and Count Latch
Registers (low byte, high byte, low byte followed by high byte).
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