CHAPTER 4. INTERRUPT CONTROLLER
The ZT 8905 includes two Intel-compatible 8259 cascaded interrupt controllers that provide a
programmable interface between interrupt-generating peripherals and the CPU. The interrupt
controllers monitor 15 interrupts with programmable priority. When peripherals request service, the
interrupt controller interrupts the CPU with a pointer to a service routine for the highest priority device.
The major features of the interrupt architecture are listed below. The ZT 8905 does not support
cascaded interrupt controllers on the STD bus or slot-specific interrupts.
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15 individually maskable interrupts
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Jumperless configuration
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Level-triggered or edge-triggered recognition
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Fixed or rotating priorities
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PCI Interrupt support
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PCI Extended Mode register support
The interrupt architecture is illustrated in the "Interrupt Architecture" figure on the following page.
Interrupt configuration is performed through screen 2 of the BIOS SETUP utility (discussed in
Appendix A) and allows the user to set up the interrupt architecture to the needs of the application.
The SETUP utility allows most of the interrupt controller interrupts to be configured from a variety of
interrupt sources. The ZT 8905 supports the Extended Mode register, which allows individual
programming of low-level triggered or active high-edge triggered interrupts.
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