Chapter 5. Counter/Timers
43
High Byte
7
6
5
4
3
2
1
0
Register: Count High
Address: 40h + Channel
Access: Read and Write
Count Register High Byte
Low Byte
7
6
5
4
3
2
1
0
Register: Count Low
Address: 40h + Channel
Access: Read and Write
Count Register Low Byte
Status Register
Each counter/timer has a Status Register. The Status Register must be read using the multiple latch
command specified in the Multiple Latch Control Register (see end of this chapter).
7
6
5
4
3
2
1
0
Register: Status
Address: 40h + Channel
Count Format
BCD
Access: Write
Access
0 Binary
Select
Mode
1 BCD
Operating Mode
000 Terminal count interrupt (Mode 0)
001 Retriggerable one-shot (Mode 1)
010 Rate generator (Mode 2)
011 Square wave generator (Mode 3)
100 Software strobe (Mode 4)
101 Hardware strobe (Mode 5)
110 Same as "010"
111 Same as "011"
Access Mode
00 Count latch command
01 Low byte only
10 High byte only
11 Low byte followed by high byte
Select Counter
00 Counter 0
01 Counter 1
10 Counter 2
11 Read back
Status Register
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