Chapter 4. Interrupt Controller
35
Initialization Register ICW1
0
0
7
6
5
4
3
2
1
0
0
1
Register
: ICW1
Address: Base+1
Initialize ICW4
0 Disabled
1 Enabled
Input Trigger
0 Edge Triggered
1 Level triggered
LTIM
0
0
1
Access:Write
Initialization Register ICW1
Initialization Register ICW2
7
6
5
4
3
2
1
0
Register: ICW2
Address: Base+1
Vector Pointer
0
Access: Write
Vector
Upper 5 bits of pointer
0
0
Initialization Register ICW2
Initialization Register ICW3
Register: Master ICW3
Address: Base + 1
Access: Write
0
0
0
0
0
1
0
0
7
6
5
4
3
2
1
0
Master Initialization Register ICW3
Register: Slave ICW3
Address: Base + 1
Access: Write
0
0
0
0
0
0
1
0
7
6
5
4
3
2
1
0
Slave Initialization Register ICW3
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