Chapter 11. System Registers
76
System Register 1
7
6
5
4
3
2
1
0
RSV
WDT
STD EXP INT
PRM
Permanent Master Operation (Read Only)
Read = Indeterminite
Write = 0
0 Temporary
1 Permanent
STD Bus NMI (Read Only)
0 Active
1 Inactive
STAR SYSTEM Interrupt
Watchdog Timer Strobe
0 Strobe Watchdog (Default)
1 Arm Watchdog
Reserved
Register: System Register 1
Address: 878h
Access: Write/Read
0 Inactive
1 Drive Interrupt
Exp. Socket SRAM/ROM Select
0 ROM
1 Emulation RAM
System Register 1
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