Chapter 6. DMA Controller
48
8905F06-01
DRQ2
8
DRQ5
16
DACK2*
8
DACK5*
16
BIOS SETUP
CONFIGURABLE
BUSRQ*
BUSAK*
DRQ0
8
DACK0*
8
ECP DRQ
ECP DACK*
DRQ1
8
DACK1
8
DRQ6
16
DACK6
16
DRQ7
16
DACK7
16
DRQ3
8
DACK3
8
NC
NC
DRQ4
16
DACK4
16
J5 PIN 52 DRQ*
J5 PIN 54 DACK*
J5 MULTI I/O
IEEE 1284 PARALLEL PORT
STD 32 BACKPLANE
(DEFAULT FOR STD 32 FLOPPY DISK
CONTROLLER SUPPORT)
INTERNAL CASCADE CHANNEL -
NOT AVAILABLE
J5 PIN 51 DRQ*
J5 PIN 53 DACK*
J5 PIN 55 DRQ*
J5 PIN 57 DACK*
†
†
† Not connected by default. Consult Cuttable Trace CT1, CT2 (Frontplane DMA) in Appendix A for details.
DMA Architecture
PROGRAMMABLE REGISTERS
Each DMA controller is managed through the 16 I/O port addresses shown in the "Slave DMA I/O
Port Addressing" table. Page registers extend the 16-bit DMA address to the full 24-bit address
space available on the ZT 8905. I/O port addressing for the DMA page registers is given in the "DMA
Page I/O Port Addressing" and "DMA Extended Page (A24-31) I/O Port Addressing" tables. These
tables are shown on the following page.
The topics that follow illustrate the DMA controller programmable registers.
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