Chapter 6. DMA Controller
50
Address Register
Register: Address
Address
A7
A6
A5
A4
A3
A2
A1
A0
7
6
5
4
3
2
1
0
Access: Read and Write
A15
A14
A13
A12
A11
A10
A9
A8
7
6
5
4
3
2
1
0
Address Register (8-bit I/O)
When programming a DMA channel configured for 16-bit I/O, the address is shifted as shown below.
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
Register: Address
Address
Access: Read and Write
A8
A7
A6
A5
A4
A3
A2
A1
A16
A15
A14
A13
A12
A11
A10
A9
†
Address Register (16-bit I/O)
† See the "Slave DMA I/O Port Addressing" table on the previous page.
Count Register
Register: Count
Address
C7
C6
C5
C4
C3
C2
C1
C0
7
6
5
4
3
2
1
0
Access: Read and Write
C15
C14
C13
C12
C11
C10
C9
C8
7
6
5
4
3
2
1
0
Count Register
† See the "Slave DMA I/O Port Addressing" table on the previous page.
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