Chapter 6. DMA Controller
53
Write Mode Register
XFR
MOD
7
6
5
4
3
2
1
0
Register: Write Mode
Slave Address: B
Mode Channel
Master Address D6
00 Channel 0
ADD
AIN
01 Channel 1
10 Channel 2
11 Channel 3
Transfer
01 Write
10 Read
11 Do not use
Autoinitialize
0 Disable
1 Enable
Address Direction
0 Increment
1 Decrement
Operating Mode
00 Demand
01 Single
MCH
Access: Write
00 Verify
10 Block
11 Cascade
Write Mode Register
DMA Extended Mode Register
ADD
RSV
7
6
5
4
3
2
1
0
Register: Ext. Mode
Slave Address: 40Bh
DMA Channel Select
Master Address: 4D6h
00 Channel 0 (4)
DMA TIM
01 Channel 1 (5)
10 Channel 2 (6)
11 Channel 3 (7)
Addressing Mode
01 16 bit, I/O count by words
10 Reserved
11 16 bit I/O, count by bytes
DMA Cycle Timing Mode (# Clocks)
00 Compatible (9 single/8 block)
01 Type A (7 single/6 block)
Reserved (Must be 0)
Reserved (Must be 0)
DMA SEL
Access: Write
00 8 bit I/O, count by bytes
EOP
10 Type B (6 single/5 block)
11 Type F (3 single/2 block)
DMA Extended Mode Register
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