1-7
SM 701730-01E
1
Principles of Operation
Analog Boar
d Assemb
ly
GND/
MES
1/1,1/10,
1/100,1/200
A
C/DC
1 M
Ω
/
50
Ω
DC/AC/
HFrej
Gain
Filter
(20 MHz,
100 MHz)
Offset
T
rig
g
er Le
vel
CH1
CH2
EXT
.
CH1/CH2
AD2 Boar
d Assemb
ly
Contr
ol
Signal
AFC
FTL
TVC
PWD
Time
Base
AT
T
One Chip Amplifier
Coupling
(A
C/DC)
Coupling
(1 M
Ω
/
50
Ω
)
Multiple
x
e
r
TV T
rig
g
e
r
Comparator
TRIG OUT
*
T
o
A
CQ2 Boar
d
Assemb
ly
PR
OBE
PO
WER
×
2 (/P2)
Fr
om P
o
wer
Unit *
Line T
rig
g
e
r
A/D
Con
ver
ter
A/D
Con
ver
ter
Cloc
k
Cloc
k
1/1
1/10
ET2 Boar
d Assemb
ly
Coupling
(GND/
MES)
Comparator
Figure 1.1 Block Diagram (Analog Section) of the DL1720E
1.3 Function of Each ASIC
