1-3
SM 701730-01E
1
Principles of Operation
AD4 Board (or AD2 Board for the DL1720E) Assembly
The AD4 board (or AD2 board for the DL1720E) assembly has the time base, trigger, A/D
converter, and analog control circuits onboard.
The time base is of a PLL configuration. 1 GHz and 800 MHz can be switched. On the
DL1720E/DL1740E/DL1740EL, the frequency of the clock is converted to 500 MHz or
400 MHz using high-speed ECL logic and distributed to each channel. When in
interleave mode, the clock for CH2 and CH4 is delayed by 1 ns with respect to the clock
for CH1 and CH3, respectively (the DL1720E is not equipped with CH3 and CH4). For
making minute time measurements of phase difference between the trigger and
sampling clock (needed during repetitive sampling mode, for example), the T-V converter
(TVC) is used.
The trigger section consists of a comparator, fast trigger logic (FTL), and pulse width
detector (PWD). It also has a TV trigger circuit used only on CH1. The comparator has
a window comparator function that allows window triggering. The window width is
controlled by an external DC voltage input. The frequency bandwidth of the comparator
IC is approximately 1 GHz.
The A/D converter operates at 500 MHz only when the sampling rate is 500 MS/s or
when in 1 GS/s interleave mode. In all other cases, the A/D converter operates at 400
MHz. Sampling rates of 200 MS/s or lower are attained by extracting a portion of the
data sampled at 400 MHz using the RBC on the ACQ4 board (or the ACQ2 board for the
DL1720E) assembly.
The analog control circuit consists of an analog front-end controller (AFC), a PWM D/A
converter, and a serial/parallel converter. This circuit controls the analog section of the
analog board assembly and the AD board assembly. There are also EXT CLOCK IN,
EXT TRIG IN, and TRIG GATE IN functions, as well as an active probe power supply (/
P4 or /P2 for the DL1720E) circuit.
ACQ4 Board (or ACQ2 Board for the DL1720E) Assembly
The ACQ4 board (or the ACQ2 board for the DL1720E) assembly has a primary data
processing section, a secondary data processing section, and a display section (for
displaying waveforms and other information).
The primary data processing section consists of the ring buffer memory (PBSRAM) and
controller (RBC). The RBC receives the data that is transferred from the A/D converter
on the ACQ4 board (or the ACQ2 board for the DL1720E) assembly and performs the
primary data processing such as the above-mentioned data extraction of sampled data,
envelope, and box averaging, then stores the data in the ring buffer memory. The
written data are transferred to the acquisition memory interface (AMI) in the secondary
data processing section according to the trigger address. The DL1720E uses 2 Mbit
PBSRAM for the ring buffer memory, the DL1740E uses 4 Mbit PBSRAM, and the
DL1740EL uses 16 Mbit PBSRAM.
The secondary data processing section consists of the AMI, work memory (PBSRAM),
and the acquisition memory (synchronous DRAM). The AMI processes the data
(averaging, for example) that is transferred from the RBC and stores the result in the
acquisition memory. Then, the AMI converts the stored data to display data by
performing additional processing such as compression and interpolation. The resultant
data are transferred to the graphic control process (GCP) on the CPU board assembly
according to the display update interval. The AMI also has computation functions
(addition, subtraction, multiplication, division, differentiation, integration, etc.) and
auxiliary functions such as automated measurement of waveform parameters.
1.2 Function of Each Assembly
