1-9
SM 701730-01E
1
Principles of Operation
Analog Boar
d Assemb
ly
GND/
MES
1/1,
1/10,
1/100,
1/200
A
C/DC
1 M
Ω
/
5
0
Ω
DC/A
C/
HFrej
Gain
Filter
(20 MHz,
100 MHz)
Offset
Line T
rig
g
e
r
T
rig
g
er Le
vel
CH1
CH2
CH3
CH4
CH1/CH2
CH3/CH4
AD4 Boar
d Assemb
ly
Contr
ol Signal
AFC
FTL
TVC
PWD
Time Base
AT
T
One Chip Amplifier
Coupling
(A
C/DC)
Coupling
(1 M
Ω
/
50
Ω
)
Multiple
x
e
r
TV T
rig
g
e
r
Comparator
EXT CLOCK IN
EXT TRIG
IN
TRIG GA
TE IN
TRIG OUT
*
T
o
A
CQ4 Boar
d
Assemb
ly
*
T
o
A
CQ4 Boar
d
Assemb
ly
PR
OBE
PO
WER
×
4 (/P4)
STL
Fr
om P
o
wer
Unit *
OPT
TRIG Boar
d Assemb
ly
A/D
Con
ver
ter
A/D
Con
ver
ter
A/D
Con
ver
ter
A/D
Con
ver
ter
Cloc
k
Cloc
k
Cloc
k
Coupling
(GND/
MES)
Figure 1.3 Block Diagram (Analog Section) of the DL1740E/DL1740EL
1.3 Function of Each ASIC
