Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
342
UG586 November 30, 2016
Chapter 2:
QDR II+ Memory Interface Solution
Design Guidelines
Design Rules
Memory types, memory parts, and data widths are restricted based on the selected FPGA,
FPGA speed grade, and the design frequency. The final frequency ranges are subject to
characterization results.
For general PCB routing guidelines, see
Appendix A, General Memory Routing Guidelines
.
ADDR_CTL_MAP
Bank and byte lane position
information for Address byte
groups. Address requires three byte
groups and this parameters
denotes the byte groups in which
all 3 Address byte groups are
selected. See the
description. This parameter varies
based on the pinout and should
not
be changed manually in
generated design.
See the
example.
D0_MAP, D1_MAP,
D2_MAP, D3_MAP,
D4_MAP, D5_MAP,
D6_MAP, D7_MAP
Bank and byte lane position
information for the Data Write bus.
See the
description. This
parameter varies based on the
pinout and should
not
be changed
manually in generated design.
See the
example.
BW_MAP
Bank and byte lane position
information for the Byte Write. See
description. This
parameter varies based on the
pinout and should
not
be changed
manually in generated design.
See the
example.
Q0_MAP, Q1_MAP,
Q2_MAP, Q3_MAP,
Q4_MAP, Q5_MAP,
Q6_MAP, Q7_MAP
Bank and byte lane position
information for the Data Read bus.
See the
description. This
parameter varies based on the
pinout and should
not
be changed
manually in generated design.
See the
example.
Table 2-13:
QDR II+ SRAM Memory Interface Solution Pinout Parameters
(Cont’d)
Parameter
Description
Example