Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
528
UG586 November 30, 2016
Chapter 4:
LPDDR2 SDRAM Memory Interface Solution
Creating 7 Series FPGA LPDDR2 SDRAM Memory Controller Block Design
Memory Selection
This page displays all memory types that are supported by the selected FPGA family.
1. Select the
LPDDR2
SDRAM
controller type.
2. Click
Next
to display the
Controller Options
page (
Controller Options
This page shows the various controller options that can be selected (
).
TIP:
The use of the Memory Controller is optional. The Physical Layer, or PHY, can be used without the
Memory Controller. The Memory Controller RTL is always generated by the MIG tool, but this output
need not be used. Controller only settings such as ORDERING are not needed in this case, and the
defaults can be used. Settings pertaining to the PHY, such as the Clock Period, are used to set the PHY
parameters appropriately.
X-Ref Target - Figure 4-16
Figure 4-16:
Memory Type and Controller Selection