Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1
381
UG586 November 30, 2016
Chapter 3:
RLDRAM II and RLDRAM 3 Memory Interface Solutions
3. Click
Next
to proceed to the
Project Name
page (
). Enter the
Project Name
and
Project Location
. Based on the details provided, the project is saved in the
directory.
X-Ref Target - Figure 3-2
Figure 3-2:
Create a New Vivado Tool Project
X-Ref Target - Figure 3-3
Figure 3-3:
Project Name