34
ML628 IBERT Getting Started Guide
UG806 (v1.0) May 20, 2011
IBERT Demonstration Designs
For additional details on this file, see:
•
http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_1/xst.pdf
,
UG627 -
XST User Guide for Virtex-4, Virtex-5, Spartan-3, and Newer CPLD Devices
example_implement_ibert_v6_q1xx.xst
The
example_implement_ibert_v6_q1xx.xst
file contains the arguments that are
passed to the xst synthesis application when the application is run in command line (i.e.,
script) mode.
For details on the arguments used in this file, see:
•
http://www.xilinx.com/support/documentation/sw_manuals/xilinx13_1/xst.pdf
,
UG627 -
XST User Guide for Virtex-4, Virtex-5, Spartan-3, and Newer CPLD Devices
i2c_sclk2_control.ngc
The
i2c_sclk2_control.ngc
file is a binary implementation netlist file containing the
logic and constraints required for the FPGA to control the SuperClock-2 module over an
I
2
C interface. The SuperClock-2 frequency table is also contained in this module. A black
box interface (
i2c_sclk2_control_bb.v
) is provided for synthesis, but the underlying
HDL source code is not provided in the design package.
ibert_v6_q1xx.ngc
The
ibert_v6_q1xx.ngc
file is a binary implementation netlist file containing the logic
and constraints required to implement the ChipScope IBERT core in an FPGA.
ibert_v6_q1xx.ngc
is created using the ISE Design Suite CORE Generator™. In the
ML628 IBERT demonstration designs, each IBERT core is configured to support a single
GTH or GTX Quad. For example,
ibert_v6_q117.ngc
is the GTH IBERT core for Quad
117. The flows for building the GTH and GTX IBERT cores for the demonstration designs
are provided in
Creating the GTH IBERT Core, page 36
For additional information on ChipScope IBERT cores, refer to following documents:
•
www.xilinx.com/support/documentation/sw_manuals/xilinx13_1/
chipscope_pro_sw_cores_ug029.pdf
, UG029 -
ChipScope Pro Software Cores
•
http://www.xilinx.com/support/documentation/ip_documentation/
chipscope_ibert_virtex6_gth.pdf
, DS755 -
ChipScope Integrated Bit Error Ratio Test
(IBERT) for Virtex-6 GTH
.
•
http://www.xilinx.com/support/documentation/ip_documentation/
chipscope_ibert_virtex6_gtx.pdf
, DS732 -
ChipScope Integrated Bit Error Ratio Test
(IBERT) for Virtex-6 GTX
.
icon_v6_1.ngc
The
icon_v6_1.ng
c file is a binary implementation netlist file containing the logic and
constraints required to implement the ChipScope Integrated Control (ICON) core in an
FPGA. This file is created using the ISE Design Suite CORE Generator. In the ML628 IBERT
demonstration designs, the ICON core is configured with a single control port which
connects to the SuperClock-2 VIO core
vio_v6_si84_so78.ngc
. The ICON core is
required to control the SuperClock-2 VIO core from the ChipScope software.
For additional details on the ChipScope ICON core, refer to:
