Xilinx ML628, Getting Started Manual

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ML628 IBERT Getting Started Guide www.xilinx.com 9
UG806 (v1.0) May 20, 2011
Running the GTH IBERT Demonstration
Transmitter pairs TX0 and TX1 on Quad 116 are not connected to the BullsEye connector
pads. Refer to
UG771 , ML628 Virtex-6 FPGA GTX and GTH Transceiver Characterization
Board User Guide for details on accessing these signals.
The SuperClock-2 module provides LVDS clock outputs for the GTH and GTX transceiver
reference clocks in the IBERT demonstrations.
Figure 1-3 shows the locations of the
differential clock SMA connectors on the clock module which can be connected to the
reference clock cables. The four SMA pairs labeled CLKOUT provide LVDS clock outputs
from the Si5368 clock multiplier/jitter attenuator device on the clock module. The SMA
pair labeled Si570_CLK provides LVPECL clock output from the Si570 programmable
oscillator on the clock module. For the GTH IBERT demonstration, the output clock
frequencies are preset to 174.690 MHz. For more information regarding the SuperClock-2
module, refer to
UG770 , HW-CLK-101-SCLK2 SuperClock-2 Module User Guide .
Note:
The image in Figure 1-3 is for reference only and might not reflect the current revision of the
board.
Attach the GTH Quad Connector
Attach the Samtec BullsEye connector to the connector pad for GTH Quad 117 ( Figure 1-4 ),
aligning the two indexing pins on the bottom of the connector with the guide holes on the
board. Hold the connector flush with the board and fasten it by tightening the two captive
screws.
X-Ref Target - Figure 1-3
Figure 1-3: SuperClock-2 Module Output Clock SMA Locations
UG725_c1_03_102010
CLKOUT3_ N CLKOUT1_ N SI570_CLK_ N
SI570_CLK_P CLKOUT1_P
CLKOUT2_ N CLKOUT4_ N
CLKOUT2_P CLKOUT3_P CLKOUT4_P
X-Ref Target - Figure 1-4
Figure 1-4: BullsEye Connector Attached to Quad 117
UG 8 06_c1_04_022411