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ML628 IBERT Getting Started Guide

www.xilinx.com

UG806 (v1.0) May 20, 2011

Creating the GTX IBERT Core

Next in the Project Options window, click on

Generation

and select the parameters

listed here:

•

Design Entry:

Verilog

•

Vendor:

Other

•

Netlist Bus Format:

B<n:m>

•

Preferred Simulation Model:

Structural

•

ASY Symbol File:

unchecked

Figure 1-38

shows the correct settings.

Click

to close the Project Options window.

In the IP Catalog pane of the CORE Generator window (

Figure 1-49

) select:

Debug & Verification

→

ChipScope Pro

→

IBERT Virtex6 GTX (ChipScope Pro - IBERT) 2.05.a

X-Ref Target - Figure 1-48

Figure 1-48:

CORE Generator Project Options (Generation Options)

06_c1_4

_041411

Summary of Contents for ML628

Page 1: ...ML628 IBERT Getting Started Guide ISE 13 1 UG806 v1 0 May 20 2011...

Page 2: ...use of the Materials including for any direct indirect special incidental or consequential loss or damage including loss of data profits goodwill or any type of loss or damage suffered as a result of...

Page 3: ...e Information 20 Running the GTX IBERT Demonstration 20 Connecting the GTX Transceivers and Reference Clocks 20 Attach the GTX Quad Connector 22 GTX Transceiver Clock Connections 22 GTX TX RX Loopback...

Page 4: ...4 www xilinx com ML628 IBERT Getting Started Guide UG806 v1 0 May 20 2011 vio_sclk2_control v 36 Creating the GTH IBERT Core 36 Creating the GTX IBERT Core 43 Warranty 51...

Page 5: ...detail in UG771 ML628 Virtex 6 FPGA GTX and GTH Transceiver Characterization Board User Guide The IBERT demonstrations operate one GTH or GTX Quad at a time Separate procedures are provided for GTH an...

Page 6: ...or higher Software is available at http www xilinx com chipscopepro The hardware and software required to rebuild the IBERT demonstration designs are Xilinx ISE Design Suite version 13 1 or higher PC...

Page 7: ...nx com products boards ml628 reference_designs htm ml628_cpj zip contains two project files ml628_gth cpj and ml628_gtx cpj These files are used to load pre saved MGT IBERT and SuperClock 2 module con...

Page 8: ...th Samtec BullsEye connectors Figure 1 2 A shows the connector pad Figure 1 2 B shows the connector pinout X Ref Target Figure 1 1 Figure 1 1 GTH Quad Locations UG806_c1_01_041411 QUAD_117 QUAD_118 QU...

Page 9: ...ECL clock output from the Si570 programmable oscillator on the clock module For the GTH IBERT demonstration the output clock frequencies are preset to 174 690 MHz For more information regarding the Su...

Page 10: ...OUT1_N are used here as an example GTH TX RX Loopback Connections Refer to Figure 1 2 page 8 to identify the P and N coax cables that are connected to the four receivers RX0 RX1 RX2 and RX3 and the fo...

Page 11: ...e online as collection rdf0116_13 1 zip at http www xilinx com products boards ml628 reference_designs htm To configure from the CF card 1 Insert the CF card labeled IBERT 1 into the CF card reader sl...

Page 12: ...X Quad on the ML628 board for a total of 16 designs The designs are organized and stored on the two CF cards IBERT 1 and IBERT 2 as shown in Table 1 1 5 Place the main power switch SW1 to the ON posit...

Page 13: ...documentation sw_manuals xilinx13_1 chipscope_pro_sw_cores_ug029 pdf UG029 ChipScope Pro Software Cores 3 Click the Open Cable button Figure 1 9 4 When the dialog opens asking to set up the core with...

Page 14: ...ad the core which is described later in this procedure This limitation will be fixed in a later release Note Unlike the Si5368 the Si570 on the SuperClock 2 module is an always on clock source As such...

Page 15: ...Project Panel double click VIO Console Figure 1 13 2 The clock sources on the SuperClock 2 module are controlled from the VIO Console Click on the Si5368 Start button Figure 1 14 to enable the clock o...

Page 16: ...prompted Do not power down the board 4 Press and release the System ACE controller reset button SW2 on the ML628 board to reload the GTH IBERT demonstration design 5 Restart the ChipScope application...

Page 17: ...he settings from the current project click Yes Figure 1 16 Note Restarting the SuperClock 2 module is not required The Si5268 clock outputs will be enabled and running at the correct frequency X Ref T...

Page 18: ...he IBERT demonstration is configured and running The status and test settings are displayed on the MGT IBERT Settings tab in the IBERT Console shown in Figure 1 19 Note the line rate TX differential o...

Page 19: ...ter clicking the BERT Reset buttons additional tuning of the transceivers might be required and or one or more DC blocks might need to be installed in line with the loopback cables See DC Blocks for i...

Page 20: ...and GTH IBERT core can be found in www xilinx com support documentation sw_manuals xilinx13_1 chipscope_pro_sw_cores_ug029 pdf UG029 ChipScope Pro Software Cores http www xilinx com support documentat...

Page 21: ...23 A shows the connector pad Figure 1 23 B shows the connector pinout X Ref Target Figure 1 22 Figure 1 22 GTX Quad Locations UG806_c1_22_041411 QUAD_104 QUAD_103 QUAD_100 QUAD_101 QUAD_102 QUAD_115 Q...

Page 22: ...d and fasten it by tightening the two captive screws GTX Transceiver Clock Connections Refer to Figure 1 22 page 21 to identify the P and N coax cables that are connected to the two reference clock in...

Page 23: ...Adapter RX1_N TX2_P SMA F F Adapter RX2_P TX2_N SMA F F Adapter RX2_N TX3_P SMA F F Adapter RX3_P TX3_N SMA F F Adapter RX3_N X Ref Target Figure 1 25 Figure 1 25 SMA F F Adapter X Ref Target Figure...

Page 24: ...as collection rdf0116_13 1 zip at http www xilinx com products boards ml628 reference_designs htm To configure from the CF card 1 Insert the CF card labeled IBERT 2 into the CF card reader slot locat...

Page 25: ...igns are organized and stored on the two CF cards IBERT 1 and IBERT 2 as shown in Table 1 1 page 12 5 Place the main power switch SW1 to the ON position Setting Up the ChipScope Pro Software 1 Start t...

Page 26: ...use an integrated ChipScope Pro software VIO core to control the clocks on the SuperClock 2 module The SuperClock 2 module features two clock source components 1 An always on Si570 crystal oscillator...

Page 27: ...i e Si5368 ROM Addr and Si570 ROM Addr are preset to 2 to produce an output frequency of 162 500 MHz Entering a different ROM address changes the reference clock s frequency The complete list of pre p...

Page 28: ...the SuperClock 2 Module the IBERT demonstration is configured and running The status and test settings are displayed on the MGT IBERT Settings tab in the IBERT Console shown in Figure 1 35 Note the l...

Page 29: ...cope_pro_sw_cores_ug029 pdf UG029 ChipScope Pro Software Cores http www xilinx com support documentation ip_documentation chipscope_ibert_virtex6_gth pdf DS755 ChipScope Integrated Bit Error Ratio Tes...

Page 30: ...on Additional information on the ChipScope Pro software and GTH IBERT core can be found in www xilinx com support documentation sw_manuals xilinx13_1 chipscope_pro_sw_cores_ug029 pdf UG029 ChipScope P...

Page 31: ...91 520 40 OTU 1 666 750 70 Generic 666 667 11 Display Port 67 500 41 OTU 2 167 330 71 Generic 205 000 12 Display Port 81 000 42 OTU 2 669 310 72 Generic 210 000 13 Display Port 135 000 43 OTU 3 168 05...

Page 32: ...Generic 375 000 118 Generic 440 000 93 Generic 315 000 106 Generic 380 000 119 Generic 445 000 94 Generic 320 000 107 Generic 385 000 120 Generic 450 000 95 Generic 325 000 108 Generic 390 000 121 Ge...

Page 33: ...o78 ngc src chipscope v example_ibert_v6_q100 v i2c_sclk2_control_bb v ibert_v6_q100_top ucf vio_sclk2_control v The par directory contains the project input and pre compiled ngc files required to bui...

Page 34: ...t_v6_q1xx ngc is created using the ISE Design Suite CORE Generator In the ML628 IBERT demonstration designs each IBERT core is configured to support a single GTH or GTX Quad For example ibert_v6_q117...

Page 35: ...top click the Start button and select Run 2 When the Run dialog box appears enter cmd in the Open field 3 Click OK to open the DOS shell From the DOS shell navigate to the directory containing the imp...

Page 36: ...trol v The vio_sclk2_control v file provides the interface between the ChipScope Virtual IO VIO and the SuperClock 2 control module i2c_sclk2_control ngc For this reason the ChipScope VIO core vio_v6_...

Page 37: ...e Project Options window click on Part and select the parameters listed here Family Virtex6 Device xc6vhx380t Package ff1923 Speed Grade 2 Figure 1 37 shows the correct settings X Ref Target Figure 1...

Page 38: ...Netlist Bus Format B n m Preferred Simulation Model Structural ASY Symbol File unchecked Figure 1 38 shows the correct settings 6 Click OK to close the Project Options window 7 In the IP Catalog pane...

Page 39: ...seconds page 1 of the IP customization window will appear Enter the information shown here and in Figure 1 40 then click Next Component Name ibert_v6_q117 Generate Bitstream unchecked Add RXUSERCLK pr...

Page 40: ...the information shown here and in Figure 1 41 then click Next Protocol OTU4 Refclk MHz 174 69 GTH count 4 X Ref Target Figure 1 40 Figure 1 40 CORE Generator IBERT GTH Customization Page 1 X Ref Targ...

Page 41: ...then click Next Select Protocol for Quad117 OTU4 11 18 Gps 12 Enter the information shown here and in Figure 1 43 then click Next Quad_117 MGTREFCLK 117 X Ref Target Figure 1 42 Figure 1 42 CORE Gene...

Page 42: ...Figure 1 45 Review the information presented and locate the following files ibert_v6_q117 ngc example_ibert_v6_q117 v example_ibert_v6_q117_top ucf Compare the v and ucf files generated here with the...

Page 43: ...following the same series of steps For more details on generating IBERT cores refer to www xilinx com support documentation sw_manuals xilinx13_1 chipscope_pro_sw_cores_ug029 pdf UG029 ChipScope Pro S...

Page 44: ...e Project Options window click on Part and select the parameters listed here Family Virtex6 Device xc6vhx380t Package ff1923 Speed Grade 2 Figure 1 37 shows the correct settings X Ref Target Figure 1...

Page 45: ...Netlist Bus Format B n m Preferred Simulation Model Structural ASY Symbol File unchecked Figure 1 38 shows the correct settings 6 Click OK to close the Project Options window 7 In the IP Catalog pane...

Page 46: ...f the IP customization window will appear Enter the information shown here and in Figure 1 50 then click Next Component Name ibert_v6_q100 Generate Bitstream unchecked Add RXRECCLK probe unchecked GTX...

Page 47: ...the information shown here and in Figure 1 51 then click Next Max Rate Gps 6 5 Refclk MHz 162 50 GTH count 4 X Ref Target Figure 1 50 Figure 1 50 CORE Generator IBERT GTX Customization Page 1 X Ref Ta...

Page 48: ...5 Gps MGT1_110 CUSTOM1 6 5 Gps MGT2_110 CUSTOM1 6 5 Gps MGT3_110 CUSTOM1 6 5 Gps 12 Leave page 4 unchanged and click Next 13 Enter the information shown here and in Figure 1 52 then click Next MGT0_1...

Page 49: ...5 The generation process will take a few minutes When complete a Readme window will appear Figure 1 55 Review the information presented and locate the following files X Ref Target Figure 1 53 Figure 1...

Page 50: ...ibert_v6_q100_top ucf Compare the v and ucf files generated here with the identically named source files provided with the ML628 board see Source Directories and Files page 32 for details on how the S...

Page 51: ...ect or default of Customer For any breach by Xilinx of this limited warranty the exclusive remedy of Customer and the sole liability of Xilinx shall be at the option of Xilinx to replace or repair the...

Page 52: ...52 www xilinx com ML628 IBERT Getting Started Guide UG806 v1 0 May 20 2011 Warranty...

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