ML628 IBERT Getting Started Guide
35
UG806 (v1.0) May 20, 2011
IBERT Demonstration Designs
•
www.xilinx.com/support/documentation/sw_manuals/xilinx13_1/
chipscope_pro_sw_cores_ug029.pdf
, UG029 -
ChipScope Pro Software Cores
vio_v6_si84_so78.ngc
The
vio_v6_si84_so78.ngc
file is a binary implementation netlist file containing the
logic and constraints required to implement the ChipScope Virtual Input/Output (VIO)
core in an FPGA.
vio_v6_si84_so78.ngc
is created using the ISE Design Suite
CORE Generator. In the ML628 IBERT demonstration designs, a VIO core is required to
control and receive status from SuperClock-2. The VIO core is configured with 84
synchronous inputs and 78 synchronous outputs, and communicates with ChipScope
through an ICON core (
icon_v6_1.ngc
).
For additional details on the ChipScope VIO core, refer to:
•
www.xilinx.com/support/documentation/sw_manuals/xilinx13_1/
chipscope_pro_sw_cores_ug029.pdf
, UG029 -
ChipScope Pro Software Cores
implement.bat
The
implement.bat
file is a Windows (DOS) batch file used to build the IBERT
demonstration design. To use this batch, open a DOS shell:
1.
From the Windows desktop, click the
Start
button and select
Run…
2.
When the Run dialog box appears, enter
cmd
in the
Open
field.
3.
Click
OK
to open the DOS shell.
From the DOS shell, navigate to the directory containing the
implement.bat
file. To run
the build, pass the Quad number as an argument to the batch. For example, to build the
IBERT demonstration in the ML628_gth_q117 directory, enter
implement 117
on the
command line.
The batch file checks that the IBERT core (e.g.,
ibert_v6_q117.ngc
) is present in the
current directory before starting the build. The batch file also creates a results directory
where, upon successful completion of the build, the
.bit
file is placed.
The
src
directory contains the Verilog HDL source code for the design. An example of the
design hierarchy is shown here:
example_ibert_v6_q117.v
icon_v6_1.ngc
vio_sclk2_control.v
i2c_sclk2_control_bb.v
The following is a description of each source file:
example_ibert_v6_q1xx.v
The
example_ibert_v6_q1xx.v
file is the top-level source file for the IBERT
demonstration.
example_ibert_v6_q1xx.v
is a modified version of the example code
that is automatically created by the CORE Generator when the IBERT core is generated
(see
Creating the GTH IBERT Core, page 36
Creating the GTX IBERT Core, page 43
All of the top-level modules and cores for the design are instantiated in this file.
