36
ML628 IBERT Getting Started Guide
UG806 (v1.0) May 20, 2011
Creating the GTH IBERT Core
i2c_sclk2_control_bb.v
The
i2c_sclk2_control_bb.v
file is the "black box" definition for the SuperClock-2
control module. It is a black box because it provides only an interface to
i2c_sclk2_control.ngc
, but no source code is present at this level. This module is
instantiated in
vio_sclk2_control.v
.
ibert_v6_qxxx_top.ucf
The
ibert_v6_qxxx_top.ucf
file is the user constraints file (UCF) for the
demonstration.
ibert_v6_qxxx_top.ucf
is the example
.ucf
created by the
CORE Generator during the IBERT core generation, but is modified to include the system
clock, I
2
C and SuperClock-2 control pin mapping.
For additional details on the user constrains file, refer to:
http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/cgd.pdf
,
UG625 -
Constraints Guide
.
vio_sclk2_control.v
The
vio_sclk2_control.v
file provides the interface between the ChipScope Virtual
IO (VIO) and the SuperClock-2 control module,
i2c_sclk2_control.ngc
. For this
reason, the ChipScope VIO core (
vio_v6_si84_so78.ngc
) and SuperClock-2 control
module (
i2c_sclk2_control.ngc
) are instantiated here.
Creating the GTH IBERT Core
This section provides a procedure to create a single Quad GTH IBERT core using
CORE Generator software. The procedure assumes Quad 117 and the OTU4 protocol
(11.18 Gb/s line rate), but cores for any of the GTH Quads with any supported line rate can
be created following the same series of steps.
For more details on generating IBERT cores, refer to
documentation/sw_manuals/xilinx13_1/chipscope_pro_sw_cores_ug029.pdf
UG029 -
ChipScope Pro Software Cores
1.
Start the CORE Generator tool from either the ISE Project Navigator window or a
command line:
•
From the Project Navigator window, select:
Tools
→
Core Generator…
•
From a command line, enter:
coregen
2.
In the Core Generator window, click the
New Project
icon (highlighted in
).
