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Wiznet W7500, Reference Manual

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W7500x Reference Manual Version1.1.0   

 

90 / 399 

to  ‘TCP  server’  configured  by  Sn_DIPR  &  Sn_DPORT(destination 

address & port). If the connect-request is successful, the Sn_SR is 

changed to SOCK_ESTABLISHED and the Sn_IR(0) becomes ‘1’. 

 

The connect-request fails in the following three cases. 

1.  When  a  ARP

TO

  occurs  (Sn_IR(3)=‘1’)  because  the 

destination hardware address is not acquired through the 

ARP-process. 

2.  When  a  SYN/ACK  packet  is  not  received  and  TCP

TO

 

(Sn_IR(3) = ‘1 ) 

3.  When  a  RST  packet  is  received  instead  of  a  SYN/ACK 

packet. 

In these cases, Sn_SR is changed to SOCK_CLOSED. 

0x08 

DISCON 

Valid only in TCP mode. 

Regardless of ‘TCP server’ or ‘TCP client’, the DISCON command 

processes  the  disconnect-process  (‘Active  close’  or  ‘Passive 

close’). 

Active close: it transmits disconnect-request(FIN packet) to the 

connected peer 

Passive close: When FIN packet is received from peer,   

a FIN packet is replied back to the peer. 

 

When  the  disconnect-process  is  successful  (that  is,  FIN/ACK 

packet  is  received  successfully),  Sn_SR  is  changed  to 

SOCK_CLOSED.  Otherwise,  TCP

TO

  occurs  (Sn_IR(3)=‘1)=  and  then 

Sn_SR is changed to SOCK_CLOSED. 

cf> If CLOSE is used instead of DISCON, only Sn_SR is changed to 

SOCK_CLOSED without disconnect-process.   

If  a  RST  packet  is  received  from  a  peer  during  communication, 

Sn_SR is unconditionally changed to SOCK_CLOSED. 

0x10 

CLOSE 

Close Socket n. 

Sn_SR is changed to SOCK_CLOSED. 

0x20 

SEND 

SEND transmits all the data in the Socket n TX buffer. For more 

details,  please  refer  to  Socket  n  TX  Free  Size  Register 

(Sn_TX_FSR), Socket n, TX Write Pointer Register (Sn_TX_WR), and 

Socket n TX Read Pointer Register(Sn_TX_RD). 

0x21 

SEND_MAC 

Valid only in UDP mode. 

The  basic  operation  is  same  as  SEND.  Normally  SEND  transmits 

data  after  destination  hardware  address  is  acquired  by  the 

Summary of Contents for W7500

Page 1: ... Copyright 2018 WIZnet Co Ltd All rights reserved W7500x Reference Manual Version 1 1 0 http www wiznet io ...

Page 2: ...in features 29 SysTick calibration value register 29 Interrupt and exception vectors 29 7 2 Event 30 8 Power supply 31 8 1 Introduction 31 8 2 Voltage regulator 31 8 3 Low power modes 31 Sleep mode 32 Peripheral clock gating 32 9 System tick timer 33 9 1 Introduction 33 9 2 Features 33 9 3 Functional description 33 9 4 Registers Base 0xE000_E000 34 System Timer control and status register SYST_CSR...

Page 3: ...source select register ADCCLK_SSR 48 ADCCLK prescale value select register ADCCLK_PVSR 48 TIMER0CLK source select register TIMER0CLK_SSR 49 TIMER0CLK prescale value select register TIMER0CLK_PVSR 49 TIMER1CLK source select register TIMER1CLK_SSR 50 TIMER1CLK prescale value select register TIMER1CLK_PVSR 50 PWM0CLK source select register PWM0CLK_SSR 51 PWM0CLK prescale value select register PWM0CLK...

Page 4: ...rol register MIICLK_ECR 63 Monitoring Clock source select register MONCLK_SSR 64 12 5 Register map 65 13Tcp ip core Offload Engine TOE 67 13 1 Introduction 67 13 2 Features 67 13 3 Functional description 68 13 4 TOE Memory map 68 Common register map 70 Socket register map 70 Memory 71 13 5 Common register Base 0x4600_0000 73 VERSIONR TOE Version Register 73 TCKCNTR Ticker Counter Register 73 IR In...

Page 5: ...6 Sn_FRAGR Socket n Fragment offset Register 97 Sn_MSSR Socket n Maximum Segment Register 97 Sn_PORTR Socket n Source Port Register 98 Sn_DHAR Socket n Destination Hardware address Register 98 Sn_DPORTR Socket n Destination Port Number Register 99 Sn_DIPR Socket n Destination IP address Register 100 Sn_KATMR Socket n Keep Alive Timer Register 101 Sn_RTR Socket n Retry Time Register 101 Sn_RCR Sock...

Page 6: ...n select register PA_06_AFR 120 PA_07 pad alternate function select register PA_07_AFR 120 PA_08 pad alternate function select register PA_08_AFR 121 PA_09 pad alternate function select register PA_09_AFR 121 PA_10 pad alternate function select register PA_10_AFR 122 PA_11 pad alternate function select register PA_11_AFR 122 PA_12 pad alternate function select register PA_12_AFR 123 PA_13 pad alte...

Page 7: ...ect register PC_07_AFR 136 PC_08 pad alternate function select register PC_08_AFR 137 PC_09 pad alternate function select register PC_09_AFR 137 PC_10 pad alternate function select register PC_10_AFR 138 PC_11 pad alternate function select register PC_11_AFR 138 PC_12 pad alternate function select register PC_12_AFR 139 PC_13 pad alternate function select register PC_13_AFR 139 PC_14 pad alternate...

Page 8: ... Register GPIOx_ INTTYPECLR x A D 159 GPIO Interrupt Polarity Set Register GPIOx_ INTPOLSET x A D 159 GPIO Interrupt Polarity Clear Register GPIOx_ INTPOLCLR x A D 160 GPIO Interrupt Status Clear Register GPIO_ INTSTATUS INTCLEAR x A D 161 GPIO Lower Byte Masked Access Register GPIOx_ LB_MASKED x A D 161 GPIO Upper Byte Masked Access Register GPIOx_ UB_MASKED x A D 162 18 5 Register map 163 19Dire...

Page 9: ...s error clear register DMA_ERR_CLR 177 19 5 Register map 179 20Analog to digital converter ADC 180 20 1 Introduction 180 20 2 Features 180 20 3 Functional description 181 Operation ADC with non interrupt 181 Operation ADC with interrupt 183 20 4 Registers Base address 0x4100_0000 183 ADC control register ADC_CTR 183 ADC channel select register ADC_CHSEL 184 ADC start register ADC_START 185 ADC con...

Page 10: ... 6 PWM Channel 1 Registers Base address 0x4000_5100 208 Channel 1 interrupt register PWMCH1IR 208 Channel 1 interrupt enable register PWMCH1IER 208 Channel 1 interrupt clear register PWMCH1ICR 209 Channel 1 Timer Counter Register PWMCH1TCR 209 Channel 1 Prescale Counter Register PWMCH1PCR 210 Channel 1 Prescale Register PWMCH1PR 210 Channel 1 Match Register PWMCH1MR 211 Channel 1 Limit Register PW...

Page 11: ...0 226 Channel 3 interrupt register PWMCH3IR 226 Channel 3 interrupt enable register PWMCH3IER 226 Channel 3 interrupt clear register PWMCH3ICR 227 Channel 3 Timer Counter Register PWMCH3TCR 227 Channel 3 Prescale Counter Register PWMCH3PCR 228 Channel 3 Prescale Register PWMCH3PR 228 Channel 3 Match Register PWMCH3MR 229 Channel 3 Limit Register PWMCH3LR 229 Channel 3 Up Down Mode Register PWMCH3U...

Page 12: ... Channel 5 interrupt enable register PWMCH5IER 244 Channel 5 interrupt clear register PWMCH5ICR 245 Channel 5 Timer Counter Register PWMCH5TCR 245 Channel 5 Prescale Counter Register PWMCH5PCR 246 Channel 5 Prescale Register PWMCH5PR 246 Channel 5 Match Register PWMCH5MR 247 Channel 5 Limit Register PWMCH5LR 247 Channel 5 Up Down Mode Register PWMCH5UDMR 247 Channel 5 Timer Counter Mode Register P...

Page 13: ...CH7IR 262 Channel 7 interrupt enable register PWMCH7IER 262 Channel 7 interrupt clear register PWMCH7ICR 263 Channel 7 Timer Counter Register PWMCH7TCR 263 Channel 7 Prescale Counter Register PWMCH7PCR 264 Channel 7 Prescale Register PWMCH7PR 264 Channel 7 Match Register PWMCH7MR 265 Channel 7 Limit Register PWMCH7LR 265 Channel 7 Up Down Mode Register PWMCH7UDMR 266 Channel 7 Timer Counter Mode R...

Page 14: ...ad Register DUALTIMER0_1TimerLoad 284 Timer0_1 Value Register DUALTIMER0_1TimerValue 284 Timer0_1 Control Register DUALTIMER0_1TimerControl 284 Timer0_1 Interrupt Clear Register DUALTIMER0_1TimerIntClr 285 Timer0_1 Raw Interrupt Status Register DUALTIMER0_1TimerRIS 285 Timer0_1 Masked Interrupt Status Register DUALTIMER0_1TimerMIS 286 Timer0_1 Background Load Register DUALTIMER0_1TimerBGLoad 286 2...

Page 15: ...r1_0 Clock Enable Register TIMCLKEN1_0 301 Timer1_1 Clock Enable Register TIMCLKEN1_1 301 22 15 Register map 302 23Watchdog timer 302 23 1 Introduction 302 23 2 Features 302 23 3 Functional description 302 Clock 302 Interrupt and reset request 303 23 4 Watchdog timer Registers Base address 0x4000_0000 303 Watchdog timer Load Register WDTLoad 303 Watchdog timer Value Register WDTValue 304 Watchdog ...

Page 16: ...rmining Month register PREMON 319 RTC Predetermining Year register PREYEAR 319 RTC Consolidated Time0 register RTCTIME0 319 RTC Consolidated Time1 register RTCTIME1 320 24 5 Register map 321 25UART Universal Asynchronous Receive Transmit 322 25 1 Introduction 322 25 2 Features 322 25 3 Functional description 323 Baud rate calculation 325 Data transmission 326 Data receive 326 Hardware flow control...

Page 17: ...7 UART1IFLS UART1 Interrupt FIFO Level Select Register 349 UART1IMSC UART1 Interrupt Mask Set Clear Register 349 UART1RIS UART1 Raw Interrupt Status Register 351 UART1MIS UART1 Masked Interrupt Status Register 352 UART1ICR UART1 Interrupt Clear Register 353 25 7 Register map 354 26Universal Asynchronous Receive Transmit UART2 355 26 1 Introduction 355 26 2 Feature 355 26 3 Functional description 3...

Page 18: ... Status register SSP0SR 383 SSP0 Clock prescale register SSP0CPSR 384 SSP0 Interrupt mask set or clear register SSP0IMSC 384 SSP0 Raw interrupt status register SSP0RIS 385 SSP0 Masked interrupt status register SSP0MIS 385 SSP0 Interrupt clear register SSP0ICR 386 SSP0 DMA control register SSP0DMACR 386 27 5 Register map 388 27 6 SSP1 Registers Base Address 0x4000_B000 389 SSP1 Control register 0 S...

Page 19: ...reset values 216 Table 19 PWM channel 2 register map and reset values 225 Table 20 PWM channel 3 register map and reset values 234 Table 21 PWM channel 4 register map and reset values 243 Table 22 PWM channel 5 register map and reset values 252 Table 23 PWM channel 6 register map and reset values 261 Table 24 PWM channel 7 register map and reset values 270 Table 25 PWM common register map and rese...

Page 20: ...W7500x Reference Manual Version1 1 0 20 399 Table 38 SSP0 register map and reset values 388 Table 39 SSP1 register map and reset values 397 ...

Page 21: ...ck diagram 164 Figure 18 DMA ping pong cycle 168 Figure 19 ADC block diagram 181 Figure 20 The ADC operation flowchart with non interrupt 182 Figure 21 The ADC operation flowchart with interrupt 183 Figure 22 PWM block diagram 189 Figure 23 Periodic mode 190 Figure 24 one shot mode 190 Figure 25 Up count mode 190 Figure 26 Down count mode 190 Figure 27 Counter mode with rising edge 191 Figure 28 C...

Page 22: ... chart 356 Figure 55 SSP block diagram 362 Figure 56 DMA transfer waveforms 365 Figure 57 Texas Instruments synchronous serial single transfer 369 Figure 58 Texas Instruments synchronous serial continuous transfers 370 Figure 59 Motorola SPI single transfer SPO 0 and SPH 0 371 Figure 60 Motorola SPI continuous transfers SPO 0 and SPH 0 371 Figure 61 Motorola SPI single continuous transfers SPO 0 a...

Page 23: ...tor DMA Direct Memory Access EOP End Of Packet EXTINT External Interrupt GPIO General Purpose Input Output IrDA Infrared Data Association I O Input Output ICMP Internet Control Message Protocol IGMP Internet Group Management Protocol IPv4 Internet Protocol version 4 IRQ interrupt request NMI NonMaskable Interrupt PADCON Pad Controller PLL Phase Locked Loop PHY Physical Layer PPPoE Point to Point P...

Page 24: ...m configuration controller TOE TCPIPCore Offload Engine TTL Transistor Transistor Logic TCP Transmission Control Protocol UART Universal Asynchronous Receiver Transmitter USB Universal Serial Bus UDP User Datagram Protocol WOL Wake On Lan WDT Watchdog Timer ...

Page 25: ...25 399 4 2 Register Bit Conventions Each register is shown with a key indicating the accessibility of the each individual bit and the initial condition Key Bit Accessibility rw Read Write r Read Only r0 Read as 0 r1 Read as 1 W Write Only ...

Page 26: ...M0 core TCP IP Offload Engine uDMAC PL230 6channel Ten slaves Internal BOOT ROM Internal SRAM Internal Flash memory Two AHB2APB bridge which connects all APB peripherals Four AHB dedicated to 16bit GPIOs TCPIP Hardware core Ethernet IP101G System architecture and AHB Lite bus architecture shown in Figure 1 Figure 1 W7500x System Architecture ...

Page 27: ...I2Cs two SSPs Random Number Generator Real Time Clock 12bits Analog Digital Converter Clock Controller IO Configuration PAD MUX controller 5 2 Memory organization Introduction Program memory data memory registers and I O ports are organized within the same linear 4 Gbyte address space The bytes are coded in memory in Little Endian format The lowest numbered byte in a word is considered the word s ...

Page 28: ...W7500x Reference Manual Version1 1 0 28 399 Memory map Figure 2 W7500x memory map ...

Page 29: ...rface are closely coupled which enables low latency interrupt processing and efficient processing of late arriving interrupts All interrupts including the core exceptions are managed by the NVIC SysTick calibration value register The SysTick calibration value is set to 6000 which gives a reference time base of 1 ms with the SysTick clock set to 6 MHz max fHCLK 8 Interrupt and exception vectors Tab...

Page 30: ...bal interrupt 0x0000_0078 22 Settable IRQ 15 PWM1 PWM1 global interrupt 0x0000_007C 23 Settable IRQ 16 PWM2 PWM2 global interrupt 0x0000_0080 24 Settable IRQ 17 PWM3 PWM3 global interrupt 0x0000_0084 25 Settable IRQ 18 PWM4 PWM4 global interrupt 0x0000_0088 26 Settable IRQ 19 PWM5 PWM5 global interrupt 0x0000_008C 27 Settable IRQ 20 PWM6 PWM6 global interrupt 0x0000_0090 28 Settable IRQ 21 PWM7 PW...

Page 31: ...he 1 5V domain There is no power down or sleep mode 8 3 Low power modes W7500x is in RUN mode after a system or power reset There are two low power modes to save power when the CPU does not need to be kept running These modes are useful for instances like when the CPU is waiting for an external interrupt Please note that there is no power off mode for W7500x The device features two low power modes...

Page 32: ...k ON Memory clocks ON DEEPSLEEP 0 Enable WFE Wakeup event Deep Sleep mode DEEPSLEEP 1 Enable WFI Any interrupt CPU clock OFF APB Bus Clock OFF AHB Bus clock OFF Memory clocks OFF DEEPSLEEP 1 Enable WFE Wakeup event Peripheral clock gating In Run mode individual clocks can be stopped at any time to reduce power Peripheral clock gating is controlled by the CRG block Below is the list of clocks which...

Page 33: ...mer is a part of the Cortex M0 it facilitates porting of software by providing a standard timer that is available on Cortex M0 based devices The SysTick timer can be used for An RTOS tick timer which fires at a programmable rate for example 100 Hz and invokes a SysTick routine A high speed alarm timer using the core clock A simple counter Software can use this to measure time to completion and tim...

Page 34: ... zero does not assert the SysTick exception request 1 Counting down to zero to asserts the SysTick exception request 16 COUNTFLAG Returns 1 if timer counted to 0 since the last read of this register SysTick Reload Value Register SYST_RVR Address Offset 0x014 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res RELOAD 23 16 R 15 14 13 12 11 10 9 8 ...

Page 35: ... the current value of the SysTick counter A write of any value clears the field to 0 and also clears the SYST_CSR COUNTFLAG bit to 0 SysTick Calibration Value Register SYST_CALIB Address Offset 0x01C Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 NORF SKEW res res res res res res TENMS 23 16 R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TENMS 15 0 R 23 0 TENMS Reads as zero ...

Page 36: ...3 operation of mode selection Mode selection Mode Aliasing TEST BOOT 0 0 APP User code execute in Main Flash memory 0 1 ISP In this mode W7500x can support ISP function in order to control flash using serial interface When W7500x is reset by hardware it will be operated as below in embedded boot code H W reset Boot Mode Run ISP ISP Run Application APP Figure 3 operation of boot code ...

Page 37: ... memory cells that can be used for storing both code and data constants The memory organization is based on a main Flash memory block containing 512 sectors of 256byte or 32 blocks of 4Kbyte Table 4 description of Flash memory Flash area Flash memory address Size bytes Name Description Main Flash memory 0x0000 0000 0x0000 00FF 256 Sector 0 Block 0 0x0000 0100 0x0000 01FF 256 Sector 1 0x0000 0200 0...

Page 38: ...cts Peripheral_Examples Flash IAP_Example there is the IAP Example Project and the below function is supported to use IAP void DO_IAP uint32_t id uint32_t dst_addr uint8_t src_addr uint32_t size This function requests those parameters id dst_addr src_addr and size id is already defined in main c dst_addr is the flash memory address in the upper table src_addr is the buffer pointer user want to pro...

Page 39: ...AP_ERAS_CHIP or IAP_ERAS_MASS Using IAP_ERAS_CHIP or IAP_ERAS_MASS DO_IAP IAP_ERAS_CHIP 0 0 0 DO_IAP IAP_ERAS_MASS 0 0 0 12 Clock Reset generator CRG 12 1 Introduction CRG is clock reset generator block for W7500x System It provides every clock reset for all other block include CPU and peripherals CRG includes PLL and POR 12 2 Features Reset Three types of reset external reset Power reset system r...

Page 40: ...re is a PLL One PLL is integrated Input clock range is from 8MHz to 24MHz Frequency can be generated by M N OD registers refer register description Bypass option enabled There are many generated clocks for independent operating with system clock System clock FCLK ADC clock ADCCLK SSP0 SSP1 clock SSPCLK UART0 UART1 clock UARTCLK Two Timer clocks TIMCLK0 TIMCLK1 8ea PWM clocks PWMCLK0 PWMCLK7 Real t...

Page 41: ...RG block diagram External Oscillator Clock The External oscillator clock OCLK can be supplied with a 8 to 24 MHz crystal ceramic resonator oscillator In the Typical application Figure 5 𝑅𝐹 must be inserted in External oscillator clock circuit In W7500x there is no supported 𝑅𝐹 for External oscillator clock see Figure 5 ...

Page 42: ...lator RC oscillator has the advantage of providing a clock source at low cost no external components However the RC oscillator is less accurate than the external crystal or ceramic resonator Accuracy 1 at TA 25o C User don t need to calibration PLL The internal PLL can be used to multiply the External Oscillator Clock OCLK or RC Oscillator Clock RCLK PLL input can be selected by register PLL outpu...

Page 43: ...ator clock RCLK External oscillator clock 8MHz 24MHz OCLK Each generated clock has own prescaler which can be selected individually by each prescale value register FCLK ADCCLK SSPCLK UARTCLK 1 1 1 2 1 4 1 8 TIMCLK0 TIMCLK1 PWMCLK0 PWMCLK7 RTCCLK WDOGCLK 1 1 1 2 1 4 1 8 1 16 1 32 1 64 1 128 ...

Page 44: ...RCOSC enter sleep mode or not 0 normal operation 1 power down enter sleep mode PLL power down register PLL_PDR Address offset 0x010 Reset value 0x0000_0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res res PLLPD R W 0 PLLPD PLL power down r...

Page 45: ...utput enable register PLL_OER Address offset 0x018 Reset value 0x0000_0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res res PLLOEN R W 0 PLLOEN output enable register of PLL This bit written by S W to control output enable of PLL 0 Clock o...

Page 46: ... res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res res PLLIS R W 0 PLLIS select register of PLL input clock source This bit written by S W to select 0 Internal 8MHz RC oscillator clock RCLK 1 External oscillator clock OCLK 8MHz 24MHz FCLK source select register FCLK_SSR Address offset 0x030 Reset value 0x0000_0001 31 30 29 28 ...

Page 47: ...KPRE R W 1 0 FCKPRE select prescale value of FCLK clock These bits are written by S W to select 00 1 1 bypass 01 1 2 10 1 4 11 1 8 SSPCLK source select register SSPCLK_SSR Address offset 0x040 Reset value 0x0000_0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res r...

Page 48: ...bypass 01 1 2 10 1 4 11 1 8 ADCCLK source select register ADCCLK_SSR Address offset 0x060 Reset value 0x0000_0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res ADCSS R W 1 0 ADCSS ADCCLK clock source select register These bits are written b...

Page 49: ...0000_0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res T0CSS R W 1 0 T0CSS TIMCLK0 clock source select register These bits are written by S W to select clock source 00 disable clock 01 PLL output clock MCLK 10 Internal 8MHz RC oscillator c...

Page 50: ...22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res T1CSS R W 1 0 T1CSS TIMCLK1 clock source select register These bits are written by S W to select clock source 00 disable clock 01 PLL output clock MCLK 10 Internal 8MHz RC oscillator clock RCLK 11 External oscillator cloc...

Page 51: ...0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res P0CSS R W 1 0 P0CPS PWMCLK0 clock source select register These bits are written by S W to select clock source 00 disable clock 01 PLL output clock MCLK 10 Internal 8MHz RC oscillator clock ...

Page 52: ...ter PWM1CLK_SSR Address offset 0x0c0 Reset value 0x0000_0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res P1CSS R W 1 0 P1CSS PWMCLK1 clock source select register These bits are written by S W to select clock source 00 disable clock 01 PLL...

Page 53: ...11 1 128 PWM2CLK source select register PWM2CLK_SSR Address offset 0x0d0 Reset value 0x0000_0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res P2CSS R W 1 0 P2CSS PWMCLK2 clock source select register These bits are written by S W to select ...

Page 54: ...01 1 2 010 1 4 011 1 8 100 1 16 101 1 32 110 1 64 111 1 128 PWM3CLK source select register PWM3CLK_SSR Address offset 0x0e0 Reset value 0x0000_0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res P3CSS R W 1 0 P3CSS PWMCLK3 clock source selec...

Page 55: ... by S W to select 000 1 1 bypass 001 1 2 010 1 4 011 1 8 100 1 16 101 1 32 110 1 64 111 1 128 PWM4CLK source select register PWM4CLK_SSR Address offset 0x0f0 Reset value 0x0000_0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res P4CSS R W 1 ...

Page 56: ...These bits are written by S W to select 000 1 1 bypass 001 1 2 010 1 4 011 1 8 100 1 16 101 1 32 110 1 64 111 1 128 PWM5CLK source select register PWM5CLK_SSR Address offset 0x100 Reset value 0x0000_0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res re...

Page 57: ...5CPS select prescale value of PWM5CLK clock These bits are written by S W to select 000 1 1 bypass 001 1 2 010 1 4 011 1 8 100 1 16 101 1 32 110 1 64 111 1 128 PWM6CLK source select register PWM6CLK_SSR Address offset 0x110 Reset value 0x0000_0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 re...

Page 58: ...s res res res res P6CPS R W 2 0 P6CPS select prescale value of PWM6CLK clock These bits are written by S W to select 000 1 1 bypass 001 1 2 010 1 4 011 1 8 100 1 16 101 1 32 110 1 64 111 1 128 PWM7CLK source select register PWM7CLK_SSR Address offset 0x120 Reset value 0x0000_0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 1...

Page 59: ...es res res res res res res res res P7CPS R W 2 0 P7CPS select prescale value of PWM7CLK clock These bits are written by S W to select 000 1 1 bypass 001 1 2 010 1 4 011 1 8 100 1 16 101 1 32 110 1 64 111 1 128 RTC High Speed source select register RTC_HS_SSR Address offset 0x130 Reset value 0x0000_0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res ...

Page 60: ...11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res RTCPRE R W 2 0 RTCPRE select prescale value of RTCCLK_hs clock These bits are written by S W to select 000 1 1 bypass 001 1 2 010 1 4 011 1 8 100 1 16 101 1 32 110 1 64 111 1 128 RTC source select register RTC_SSR Address offset 0x13c Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res...

Page 61: ... 1 0 WDHS WDOGCLK_hs clock source select register These bits are written by S W to select clock source 00 disable clock 01 PLL output clock MCLK 10 Internal 8MHz RC oscillator clock RCLK 11 External oscillator clock OCLK 8MHz 24MHz WDOGCLK High Speed prescale value select register WDOGCLK_HS_PVSR Address offset 0x144 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res r...

Page 62: ...r These bits are written by S W to select clock source 0 WDOGCLK_hs 1 32K_OSC_CLK Low speed external oscillator clock UARTCLK source select register UARTCLK_SSR Address offset 0x150 Reset value 0x0000_0001 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res ...

Page 63: ... 01 1 2 10 1 4 11 1 8 MIICLK enable control register MIICLK_ECR Address offset 0x160 Reset value 0x0000_0003 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res MIITEN MIIREN R W R W 0 MIIREN MII RX Clock source enable register This bit is writte...

Page 64: ...es res res res res res CLKMON_SEL R W 4 0 CLKMON_SEL Select clock source for monitoring monitoring pin PA_02 This bit is written by S W to set enable or disable 00000 PLL output clock MCLK 00001 FCLK 00010 Internal 8MHz RC oscillator clock RCLK 00011 External oscillator clock OCLK 8MHz 24MHz 00100 ADCCLK 00101 SSPCLK 00110 TIMCLK0 00111 TIMCLK1 01000 PWMCLK0 01001 PWMCLK1 01010 PWMCLK2 01011 PWMCL...

Page 65: ... res res res res res res res res res res res res res res res res res res res res res res reset value 0 1 SSPCLK_PVSR res res res res res res res res res res res res res res res res res res res res res res res res res res res res res res reset value 0 0 ADCCLK_SSR res res res res res res res res res res res res res res res res res res res res res res res res res res res res res res reset value 0 1 ...

Page 66: ...PWM6CLK_SSR res res res res res res res res res res res res res res res res res res res res res res res res res res res res res res reset value 0 1 PWM6CLK_PVSR res res res res res res res res res res res res res res res res res res res res res res res res res res res res res reset value 0 0 0 PWM7CLK_SSR res res res res res res res res res res res res res res res res res res res res res res res r...

Page 67: ...d simultaneously TOE also provides WOL Wake on LAN to reduce power consumption of the system 13 2 Features Supports Hardwired TCP IP Protocols TCP UDP ICMP IPv4 ARP IGMP PPPoE Supports 8 independent sockets simultaneously Supports Power down mode Supports Wake on LAN over UDP Internal 32Kbytes Memory for TX RX Buffers Not supports IP Fragmentation UARTCLK_SSR res res res res res res res res res re...

Page 68: ...uffer Blocks Each Socket s TX Buffer Block physically exists in one 16KB TX memory and is initially allocated with 2KB Also Each Socket s RX Buffer Block physically exists in one 16KB RX Memory and is initially allocated with 2KB Regardless of the allocated size of each Socket TX RX Buffer it can be accessible within the 16 bits offset address range From 0x0000 to 0xFFFF RXC TXC RXC_N TXC_N COL DU...

Page 69: ...x0FFF 0x0000 0x1000 0x0800 0x1800 0x2000 0x2800 0x3000 0x3800 0x3FFF Socket 0 RX Buffer 2KB Socket 1 RX Buffer 2KB Socket 2 RX Buffer 2KB Socket 3 RX Buffer 2KB Socket 4 RX Buffer 2KB Socket 5 RX Buffer 2KB Socket 6 RX Buffer 2KB Socket 7 RX Buffer 2KB 0x3E2C 0x0FFF Physical 16KB TX Memory Socket 7 RX Buffer Socket 7 TX Buffer Socket 7 Register Reserved Socket 6 RX Buffer Socket 6 TX Buffer Socket...

Page 70: ...c PMAGIC 0x2408 PPP Destination MAC Address PHAR1 0x240C PPP Destination MAC address PHAR0 0x2410 PPP Session Identification PSIDR 0x2414 PPP Maximum Segment Size PMSS 0x6000 Source Hardware Address SHAR1 0x6004 Source Hardware Address SHAR0 0x6008 Gateway Address GA 0x600C Subnet Mask SUB 0x6010 Source IP Address SIP 0x6020 Network Configuration Lock NCONFL 0x6040 Retry Time RTR 0x6044 Retry Coun...

Page 71: ...ocket Destination Port Number Sn_DPORTR 0x0124 Socket Destination IP Address Sn_DIPR 0x0180 Socket Keep Alive Timer Sn_KATMR 0x0184 Socket Retry Time Sn_RTR 0x0188 Socket Retry Counter Sn_RCR 0x0200 Socket TX Memory Size Sn_TXBUF_SIZE 0x0204 Socket TX Free Size Sn_TX_FSR 0x0208 Socket TX Read Pointer Sn_TX_RD 0x020C Socket TX Write Pointer Sn_TX_WR 0x0220 Socket RX Memory Size Sn_RXBUF_SIZE 0x0224...

Page 72: ...cally determined in 16KB RX memory Therefore the total sum of Sn_RXBUF_SIZE should not exceed 16 or data reception error will occur For 16KB TX RX memory allocation refer to Sn_TXBUF_SIZE Sn_RXBUF_SIZE in Chapter 0 The Socket n TX Buffer Block allocated in 16KB TX memory is buffer for saving data to be transmitted by host The 16bits Offset Address of Socket n TX Buffer Block has 64KB address space...

Page 73: ...cates the TOE version as 0x05 TCKCNTR Ticker Counter Register Address Offset 0x2000 Reset value 0x0000_07D0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res Res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TCKCNT 15 0 R W 15 0 TCKCNT Ticker counter register is used Tick counter of 100usec for internal timer of TOE The unit of tick is HCLK RTR Sn_...

Page 74: ...PoE PPPoE Close When PPPoE is disconnected during PPPoE mode this bit is set 6 UNREACH Destination unreachable When receiving the ICMP Destination port unreachable packet this bit is set as 1 When this bit is 1 Destination Information such as IP address and Port number may be checked with the corresponding UIPR UPORTR 7 Conflict IP Conflict Bit is set as 1 when own source IP address is same with t...

Page 75: ...nreachable Interrupt 7 IP Conflict Interrupt Mask 0 Disable IP Conflict Interrupt 1 Enable IP Conflict Interrupt IRCR Interrupt Clear Register Address Offset 0x2108 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res IRC 8 4 res res res res R C_W...

Page 76: ...ntil SIR is 0x00 7 0 SIR When the interrupt of Socket n occurs the n th bit of SIR becomes 1 SIMR Socket Interrupt Mask Register Address Offset 0x2114 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res S7 S6 S5 S4 S3 S2 S1 S0 R W R W R W R W R W...

Page 77: ...lock 5 WOL Wake on Lan If WOL mode is enabled and the received magic packet over UDP has been normally processed the Interrupt PIN INTn asserts to low When using WOL mode the UDP Socket should be opened with any source port number Refer to Socket n Mode Register Sn_MR for opening Socket Notice The magic packet over UDP supported by TOE consists of 6 bytes synchronization stream 0xFFFFFFFFFFFF and ...

Page 78: ... of time is 25ms Ex in case that PTIMER is 200 200 25 ms 5000 ms 5 seconds PMAGICR PPP Link Control Protocol Magic number Register Address Offset 0x2404 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res Res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res Res res res res res PMAGIC 7 0 R W R W R W R W R W R W R W R ...

Page 79: ...W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res PHAR should be written to the PPPoE server hardware address acquired in PPPoE connection process PHAR0 and PHAR1 configures Destination hardware address Ex In case that destination hardware address is 00 08 DC 12 34 56 PHAR0 32 24 PHAR0 23 16 PHAR0 15 8 PHAR0 32 24 PHAR1 32 24 PHAR1 23 16 0x00 0x08 0xDC 0x12 0x34 0x56 PSIDR Session ID Register in...

Page 80: ...PMRUR configures the maximum receive unit of PPPoE Ex in case that maximum receive unit in PPPoE is 0x1234 PMSS 15 8 PMSS 7 0 0x12 0x34 SHAR Source Hardware Address Register Address Offset 0x6000 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SHAR0 31 24 SHAR0 23 16 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SHAR0 ...

Page 81: ...22 21 20 19 18 17 16 GA 31 24 GA 23 16 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 GA 15 8 GA 7 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W GAR 31 0 configures the default gateway address Ex In case of 192 168 0 1 GA 31 24 GA 23 16 GA 15 8 GA 7 0 192 0xC0 168 0xA8 0 0x00 1 0x01 SUBR Subnet Mask Register Address Offset ...

Page 82: ...25 24 23 22 21 20 19 18 17 16 SIPR 31 24 SIPR 23 16 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SIPR 15 8 SIPR 7 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W SIPR configures the source IP address Ex In case of 192 168 0 2 SIPR 31 24 SIPR 23 16 SIPR 15 8 SPIR 7 0 192 0xC0 168 0xA8 0 0x00 2 0x02 NCONFLR Network Configurat...

Page 83: ... 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RTR 15 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W RTR configures the retransmission timeout period The unit of timeout period is 100us Refer to TCKCNTR and the default of RTR is 0x07D0 or 2000 And so the default timeout period is 200ms 100us X 2000 During the...

Page 84: ...0 0x07 The timeout of WZTOE can be configurable with RTR and RCR WZTOE has two kind timeout such as Address Resolution Protocol ARP and TCP retransmission At the ARP Refer to RFC 826 http www ietf org rfc html retransmission timeout WZTOE automatically sends ARP request to the peer s IP address in order to acquire MAC address information used for communication of IP UDP or TCP While waiting for AR...

Page 85: ...l timeout TCPTO of TCP retransmission is as below 𝑇𝐶𝑃𝑇𝑂 𝑅𝑇𝑅 2𝑁 𝑅𝐶𝑅 𝑀 𝑅𝑇𝑅𝑀𝐴𝑋 𝑀 𝑁 0 0 1𝑚𝑠 N Retransmission count 0 N M M Minimum value when RTR x 2 M 1 65535 and 0 M RCR RTRMAX RTR x 2M Ex When RTR 2000 0x07D0 RCR 8 0x0008 ARPTO 2000 X 0 1ms X 9 1800ms 1 8s TCPTO 0x07D0 0x0FA0 0x1F40 0x3E80 0x7D00 0xFA00 0xFA00 0xFA00 0xFA00 X 0 1ms 2000 4000 8000 16000 32000 8 4 X 64000 X 0 1ms 318000 X 0 1ms 31 8s...

Page 86: ... res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 UPORT 15 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W TOE receives an ICMP packet Destination port unreachable when data is sent to a port number which socket is not open and UNREACH bit of IR becomes 1 and UPORTR indicates the destination port number 15 0 UPORT Destination port numb...

Page 87: ...ket 0 4 UNICAST Blocking and IPv6 packet Blocking UNICAST Blocking in UDP mode 0 disable Unicast Blocking 1 enable Unicast Blocking This bit blocks receiving the unicast packet during UDP mode P 3 0 0010 and MULTI 1 IPv6 packet Blocking in MACRAW mode 0 disable IPv6 Blocking 1 enable IPv6 Blocking This bit is applied only during MACRAW mode P 3 0 0100 It blocks to receiving the IPv6 packet 5 Use N...

Page 88: ...ived from a peer When this bit is 0 It sends the ACK packet after waiting for the timeout time configured by RTR 7 Multicasting and MAC Filter Enable mode Multicasting in UDP mode 0 disable Multicasting 1 enable Multicasting This bit is applied only during UDP mode P 3 0 0010 To use multicasting Sn_DIPR Sn_DPORT should be respectively configured with the multicast group IP address port number befo...

Page 89: ...N Socket n is initialized and opened according to the protocol selected in Sn_MR P3 P0 The table below shows the value of Sn_SR corresponding to Sn_MR Sn_MR P 3 0 Sn_SR Sn_MR_CLOSE 0000 Sn_MR_TCP 0001 SOCK_INIT 0x13 Sn_MR_UDP 0010 SOCK_UDP 0x22 S0_MR_MACRAW 0100 SOCK_MACRAW 0x02 0x02 LISTEN This is valid only in TCP mode Sn_MR P3 P0 Sn_MR_TCP In this mode Socket n operates as a TCP server and wait...

Page 90: ... to the connected peer Passive close When FIN packet is received from peer a FIN packet is replied back to the peer When the disconnect process is successful that is FIN ACK packet is received successfully Sn_SR is changed to SOCK_CLOSED Otherwise TCPTO occurs Sn_IR 3 1 and then Sn_SR is changed to SOCK_CLOSED cf If CLOSE is used instead of DISCON only Sn_SR is changed to SOCK_CLOSED without disco...

Page 91: ...ister Sn_RX_RD Sn_IR Socket n Interrupt Register Address Offset 0x0020 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res Res Res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res Res Res res res Res res res res res res Sn_IR 4 0 R R R R R Sn_IR indicates the status of Socket Interrupt such as establishment termination receiving ...

Page 92: ...ot be issued even if the corresponding bit of Sn_IR is 1 0 CONNECT Interrupt Mask 0 Disable CONNECT Interrupt 1 Enable CONNECT Interrupt 1 DISCONNECT Interrupt Mask 0 Disable DISCONNECT Interrupt 1 Enable DISCONNECT Interrupt 2 RECV Interrupt Mask 0 Disable RECV Interrupt 1 Enable RECV Interrupt 3 TIMEOUT Interrupt Mask 0 Disable TIMEOUT Interrupt 1 Enable TIMEOUT Interrupt 4 SENDOK Interrupt Mask...

Page 93: ... 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res Res Res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res Res Res res res res res res Sn_SR 7 0 R W R W R W R W R W R W R W R W Sn_SR indicates the status of Socket n The status of Socket n is changed by Sn_CR or some special control packet as SYN FIN packet in TCP Value Symbol Description 0x00 SOCK_CLOSED T...

Page 94: ...disconnect request FIN packet from the connected peer This is half closing status and data can be transferred For full closing DISCON command is used But For just closing CLOSE command is used 0x22 SOCK_UDP This indicates Socket n is opened in UDP mode Sn_MR P 3 0 0010 It changes to SOCK_UDP when Sn_MR P 3 0 0010 and OPEN command is ordered Unlike TCP mode data can be transfered without the connec...

Page 95: ...ve close and passive close When Disconnect process is successfully completed or when timeout occurs these change to SOCK_CLOSED 0x1A SOCK_CLOSING 0X1B SOCK_TIME_WAIT 0X1D SOCK_LAST_ACK This indicates Socket n is waiting for the response FIN ACK packet to the disconnect request FIN packet by passive close It changes to SOCK_CLOSED when Socket n received the response successfully or when timeout occ...

Page 96: ...0 res Res Res res res res res res Sn_ROS 7 0 R W R W R W R W R W R W R W R W Sn_TOSR configures the TOS Type Of Service field in IP Header of Socket n It is set before OPEN command For more the details refer to http www iana org assignments ip parameters Sn_TTLR Socket n TTL Register Address Offset 0x0108 Reset value 0x0000_0080 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res Res Res res res r...

Page 97: ...header Ex Sn_FRAGR 0x0000 Don t Fragment Sn_FRAG 15 8 Sn_FRAG 7 0 0x00 0x00 Sn_MSSR Socket n Maximum Segment Register Address Offset 0x0110 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res Res Res res res res res res res Res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Sn_MSS 15 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W This regis...

Page 98: ...efore OPEN command is ordered Ex In case of Socket 0 Port 5000 0x1388 configure as below 0x4101_0114 0x1388 Sn_DHAR Socket n Destination Hardware address Register Address Offset 0x0118 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Sn_DHAR0 31 24 Sn_DHAR0 23 16 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Sn_DHAR0 15...

Page 99: ... 7 0 0x00 0x08 0xDC 0x12 0x34 0x56 Ex In case of reading MAC address 00 08 DC 12 34 56 Sn_DHAR0 31 24 Sn_DHAR0 23 16 Sn_DHAR0 15 8 Sn_DHAR0 7 0 Sn_DHAR1 31 24 Sn_DHAR1 23 16 0x00 0x08 0xDC 0x12 0x34 0x56 Sn_DPORTR Socket n Destination Port Number Register Address Offset 0x0120 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Res Res Res res res res res res res res res res re...

Page 100: ...22 21 20 19 18 17 16 Sn_DIPR 31 24 Sn_DIPR 23 16 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Sn_DIPR 15 8 Sn_DIPR 7 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Sn_DIPR configures or indicates the destination IP address of Socket n It is valid when Socket n is used in TCP UDP mode In TCP client mode it configures an IP ...

Page 101: ...automatically transmits KA packet after time period for checking the TCP connection Auto keepalive process In case of Sn_KPALVTR 0 Auto keep alive process will not operate and KA packet can be transmitted by SEND_KEEP command by the host Manual keep alive process Manual keep alive process is ignored in case of Sn_KPALVTR 0 Ex Sn_KPALVTR 10 Keep Alive packet will be transmitted every 50 seconds Sn_...

Page 102: ...ddress Offset 0x0188 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res Res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res Sn_RC 7 0 R W R W R W R W R W R W R W R W Sn_RCR configures the number of time of retransmission of Socket n When Retry Counter Register RCR is zero Sn_RCR is valid When retransmission occurs as many as Sn_RCR 1 Timeout interrupt is issued Sn_IR TIMEOUT 1 E...

Page 103: ...fer is allocated with the configured size in 16KB TX Buffer and is assigned sequentially from Socket 0 to Socket 7 Socket n TX Buffer can be accessible with 16bits Offset Address ranged from 0x0000 to 0xFFFF regardless of the configured size Refer to Sn_TX_WR Sn_TX_RD Value dec 0 1 2 4 8 16 Buffer size 0KB 1KB 2KB 4KB 8KB 16KB Ex Socket 0 TX Buffer Size 4KB 0x4600_0200 0x04 Sn_TX_FSR Socket n TX F...

Page 104: ...een Sn_TX_WR and the internal ACK pointer which indicates the point of data is received already by the connected peer Ex In case of 2048 0x0800 in S0_TX_FSR 0x4600_0204 0x0800 Note Because this register for representing the size information is 16 bits it is impossible to read all bytes at the same time Before 16 bit read operation is not completed the value may be changed Therefore it is recommend...

Page 105: ... W R W R W R W R W R W R W R W R W R W R W Sn_TX_WR is initialized by OPEN command However if Sn_MR P 3 0 is TCP mode 0001 it is re initialized while connecting with TCP It should be read or to be updated like as follows 1 Read the starting address for saving the transmitting data 2 Save the transmitting data from the starting address of Socket n TX buffer 3 After saving the transmitting data upda...

Page 106: ...is assigned sequentially from Socket 0 to Socket 7 Socket n RX Buffer Block can be accessible with the 16bits Offset Address ranged from 0x0000 to 0xFFFF regardless of the configured size Refer to Sn_RX_RD Sn_RX_WR Value dec 0 1 2 4 8 16 Buffer size 0KB 1KB 2KB 4KB 8KB 16KB Ex Socket 0 RX Buffer Size 8KB 0x4101_0220 0x08 Sn_RX_RSR Socket n RX Received Size Register Address Offset 0x0224 Reset valu...

Page 107: ...res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Sn_RXRP 15 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Sn_RX_RD is initialized by OPEN command Make sure to be read or updated as follows 1 Read the starting save address of the received data 2 Read data from the starting address of Socket n RX Buffer 3 After reading the received data Update...

Page 108: ...15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Sn_RX_WR 15 0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Sn_RX_WR is initialized by OPEN command and it is auto increased by the data reception If the increased value exceeds the maximum value 0xFFFF greater than 0x10000 and the carry bit occurs then the carry bit is ignored and will automatically update with the lower 16bits value Ex In c...

Page 109: ...alue and polynomial of RNG can be modified by software 14 2 Features 32bit pseudo random number generator Formula of pseudo random number generator polynomial can be modified Seed value of random generator can be modified Support power on reset random value Random value can be obtains by control start stop by software 14 3 Functional description Figure 8 shows the RNG block diagram Figure 8 Random...

Page 110: ...te a random number 1 Change MODE to start stop by register 2 Change clock source seed value polynomial value if need 3 Run and Stop the RNG 4 Read Random value START Change clock source if need RNG_CLK_SEL Change seed value if need RNG_SEED Change polynomial value if need RNG_POLY Run RNG RNG_RUN 1 STOP RNG RNG_RUN 0 DONE Change RNG_MODE RNG_MODE 1 Read generated random number RN Figure 9 Flow cha...

Page 111: ...r This bit written by S W to run or stop RNG 0 stop random number generator shift register 1 run random number generator shift register RNG SEED register RNG_SEED Address offset 0x004 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SEED 31 16 R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SEED 15 0 R W 31 0 SEED seed value of random number generator shift register These bits wri...

Page 112: ...t register RNG_MODE Address offset 0x00c Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res res MODE R W 0 MODE RNG run mode select register This bit written by S W to select which mode 0 run stop by PLL_LOCK signal which...

Page 113: ...ers RNG polynomial register RNG_POLY Address offset 0x014 Reset value 0xE000_0202 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 POLY 31 16 R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 POLY 15 0 R W 31 0 POLY 32bit polynomial of random number generator These bits are written by S W to modify the formula of random number generator Default polynomial F x x31 x30 x29 x9 x ...

Page 114: ...nd Function 3rd Function 4th Function Offset Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RNG_RUN res res res res res res res res res res res res res res res res res res res res res res res res res res res res res res res RUN reset value 0 RNG_SEED reset value 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 RNG_CLKSEL res res res re...

Page 115: ...P3 W7500P 20 PA_07 W7500 35 MISO0 U_CTS1 PWM4 CAP4 W7500P 21 PA_08 W7500 36 MOSI0 U_RTS1 PWM5 CAP5 W7500P 22 PA_09 W7500 37 SCL0 U_TXD1 PWM6 CAP6 W7500P 23 PA_10 W7500 38 SDA0 U_RXD1 PWM7 CAP7 W7500P 24 PA_11 W7500 40 U_CTS0 SSEL1 W7500P 41 PA_12 W7500 41 U_RTS0 SCLK1 W7500P 42 PA_13 W7500 42 U_TXD0 MISO1 W7500P 43 PA_14 W7500 43 U_RXD0 MOSI1 W7500P 44 PA_15 W7500 44 GPIOA_15 GPIOA_15 PB_00 W7500 ...

Page 116: ...B_14 PB_15 W7500 27 GPIOB_15 GPIOB_15 PC_00 W7500 53 U_CTS1 GPIOC_0 PWM0 CAP0 W7500P PC_01 W7500 54 U_RTS1 GPIOC_1 PWM1 CAP1 W7500P PC_02 W7500 55 U_TXD1 GPIOC_2 PWM2 CAP2 W7500P PC_03 W7500 56 U_RXD1 GPIOC_3 PWM3 CAP3 W7500P PC_04 W7500 57 SCL1 GPIOC_4 PWM4 CAP4 W7500P PC_05 W7500 58 SDA1 GPIOC_5 PWM5 CAP5 W7500P PC_06 W7500 51 GPIOC_6 GPIOC_6 U_TXD2 W7500P 11 PC_07 W7500 52 GPIOC_7 GPIOC_7 U_RXD...

Page 117: ... select register PA_00_AFR Address offset 0x000 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res PA00AF R W 1 0 PA00AF PA_00 Pad alternate function selection register These bits are written by S W 00 GPIOA_0 01 GPIOA_0 ...

Page 118: ... 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res PA02AF R W 1 0 PA02AF PA_02 Pad function selection register These bits are written by S W 00 GPIOA_2 01 GPIOA_2 10 CLKOUT 11 None PA_03 pad alternate function select register PA_03_...

Page 119: ...ddress offset 0x010 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res PA04AF R W 1 0 PA04AF PA_04 Pad function selection register These bits are written by S W 00 SWDIO 01 GPIOA_4 10 None 11 PWM1 CAP1 PA_05 pad alternate...

Page 120: ...ddress offset 0x018 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res PA06AF R W 1 0 PA06AF PA_06 Pad function selection register These bits are written by S W 00 SCLK0 01 GPIOA_6 10 SDA1 11 PWM3 CAP3 PA_07 pad alternate...

Page 121: ...0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res PA08AF R W 1 0 PA08AF PA_08 Pad function selection register These bits are written by S W 00 MOSI0 01 GPIOA_8 10 RTS1 11 PWM5 CAP5 PA_09 pad alternate function select register PA_09_...

Page 122: ...x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res PA10AF R W 1 0 PA10AF PA_10 Pad function selection register These bits are written by S W 00 SDA0 01 GPIOA_10 10 RXD1 11 PWM7 CAP7 PA_11 pad alternate function select register PA_11_A...

Page 123: ...0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res PA12AF R W 1 0 PA12AF PA_12 Pad function selection register These bits are written by S W 00 RTS0 01 GPIOA_12 10 SCLK1 11 None PA_13 pad alternate function select register PA_13_AFR ...

Page 124: ...0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res PA14AF R W 1 0 PA14AF PA_14 Pad function selection register These bits are written by S W 00 RXD0 01 GPIOA_14 10 MOSI1 11 None PA_15 pad alternate function select register PA_15_AFR ...

Page 125: ... 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res PB00AF R W 1 0 PB00AF PB_00 Pad function selection register These bits are written by S W 00 SSEL1 01 GPIOB_0 10 CTS0 11 None PB_01 pad alternate function select register PB_01_AFR Address offset 0x0...

Page 126: ...s res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res PB02AF R W 1 0 PB02AF PB_02 Pad function selection register These bits are written by S W 00 MISO1 01 GPIOB_2 10 TXD0 11 None PB_03 pad alternate function select register PB_03_AFR Address offset 0x04c Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23...

Page 127: ... res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res PB04AF R W 1 0 PB04AF PB_04 Pad function selection register These bits are written by S W 00 TXEN 01 GPIOB_4 10 None 11 None PB_05 pad alternate function select register PB_05_AFR Address offset 0x054 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res ...

Page 128: ...s res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res PB06AF R W 1 0 PB06AF PB_06 Pad function selection register These bits are written by S W 00 RXD3 01 GPIOB_6 10 None 11 None PB_07 pad alternate function select register PB_07_AFR Address offset 0x05c Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res...

Page 129: ...res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res PB08AF R W 1 0 PB08AF PB_08 Pad function selection register These bits are written by S W 00 DUP 01 GPIOB_8 10 None 11 None PB_09 pad alternate function select register PB_09_AFR Address offset 0x064 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res re...

Page 130: ...es res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res PB10AF R W 1 0 PB10AF PB_10 Pad function selection register These bits are written by S W 00 TXD0 01 GPIOB_10 10 None 11 None PB_11 pad alternate function select register PB_11_AFR Address offset 0x06c Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res r...

Page 131: ...13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res PB12AF R W 1 0 PB12AF PB_12 Pad function selection register These bits are written by S W 00 TXD2 01 GPIOB_12 10 None 11 None PB_13 pad alternate function select register PB_13_AFR Address offset 0x074 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res re...

Page 132: ... res res res res res res res res res res res res PB14AF R W 1 0 PB14AF PB_14 Pad function selection register These bits are written by S W 00 MDIO 01 GPIOB_14 10 None 11 None PB_15 pad alternate function select register PB_15_AFR Address offset 0x07c Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 1...

Page 133: ...es res res res res res res PC00AF R W 1 0 PC00AF PC_00 Pad function selection register These bits are written by S W 00 CTS1 01 GPIOC_0 10 PWM0 CAP0 11 None PC_01 pad alternate function select register PC_01_AFR Address offset 0x084 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3...

Page 134: ...s res res res res res res res PC02AF R W 1 0 PC02AF PC_02 Pad function selection register These bits are written by S W 00 TXD1 01 GPIOC_2 10 PWM2 CAP2 11 None PC_03 pad alternate function select register PC_03_AFR Address offset 0x08c Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 ...

Page 135: ...s res res res res res res res PC04AF R W 1 0 PC04AF PC_04 Pad function selection register These bits are written by S W 00 SCL1 01 GPIOC_4 10 PWM4 CAP4 11 None PC_05 pad alternate function select register PC_05_AFR Address offset 0x094 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 ...

Page 136: ...res res res res res PC06AF R W 1 0 PC06AF PC_06 Pad function selection register These bits are written by S W 00 GPIOC_6 01 GPIOC_6 10 TXD2 11 None PC_07 pad alternate function select register PC_07_AFR Address offset 0x09c Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 re...

Page 137: ...res PC08AF R W 1 0 PC08AF PC_08 Pad function selection register These bits are written by S W 00 PWM0 CAP0 01 GPIOC_8 10 SCL0 11 ADC_IN7 PC_09 pad alternate function select register PC_09_AFR Address offset 0x0a4 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res r...

Page 138: ...F R W 1 0 PC10AF PC_10 Pad function selection register These bits are written by S W 00 TXD2 01 GPIOC_10 10 PWM2 CAP2 11 ADC_IN5 PC_11 pad alternate function select register PC_11_AFR Address offset 0x0ac Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res r...

Page 139: ...W 1 0 PC12AF PC_12 Pad function selection register These bits are written by S W 00 ADC_IN3 01 GPIOC_12 10 SSEL0 11 ADC_IN3 PC_13 pad alternate function select register PC_13_AFR Address offset 0x0b4 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res re...

Page 140: ...W 1 0 PC14AF PC_14 Pad function selection register These bits are written by S W 00 ADC_IN1 01 GPIOC_14 10 MISO0 11 ADC_IN1 PC_15 pad alternate function select register PC_15_AFR Address offset 0x0bc Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res re...

Page 141: ...D00AF R W 1 0 PD00AF PD_00 Pad function selection register These bits are written by S W 00 CRS 01 GPIOD_0 10 None 11 None PD_01 pad alternate function select register PD_01_AFR Address offset 0x0c4 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res...

Page 142: ...D02AF R W 1 0 PD02AF PD_02 Pad function selection register These bits are written by S W 00 RXD0 01 GPIOD_2 10 None 11 None PD_03 pad alternate function select register PD_03_AFR Address offset 0x0cc Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res re...

Page 143: ...00_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res PD04AF R W 1 0 PD04AF PD_04 Pad function selection register These bits are written by S W 00 RXD2 01 GPIOD_4 10 None 11 None ...

Page 144: ...s res res res res res res res res res res res res res res res res res res res res res res res res reset value 0 0 PA_09_AFR res res res res res res res res res res res res res res res res res res res res res res res res res res res res res res reset value 0 0 PA_10_AFR res res res res res res res res res res res res res res res res res res res res res res res res res res res res res res reset valu...

Page 145: ...AFR res res res res res res res res res res res res res res res res res res res res res res res res res res res res res res reset value 0 0 PB_13_AFR res res res res res res res res res res res res res res res res res res res res res res res res res res res res res res reset value 0 0 PB_14_AFR res res res res res res res res res res res res res res res res res res res res res res res res res res ...

Page 146: ...es res res res res res res res res res res res res res res res res res res res res reset value 0 0 PC_14_AFR res res res res res res res res res res res res res res res res res res res res res res res res res res res res res res reset value 0 0 PC_15_AFR res res res res res res res res res res res res res res res res res res res res res res res res res res res res res res reset value 0 0 PD_00_AFR...

Page 147: ...s the following functions and can be controlled by registers Interrupt mask enable or disable default disable Interrupt polarity rising or falling default rising 16 3 Functional description All pads are connected to the control register individually External interrupt mask register and External Interrupt polarity register External interrupt working as following expression Each pad interrupt Interr...

Page 148: ...PA_00 EXTINT PA_14_Polarity PA_14_mask PA_14 PB_00_Polarity PB_00_mask PB_00 PB_03_Polarity PB_03_mask PB_03 PC_00_Polarity PC_00_mask PC_00 PC_06_Polarity PC_06_mask PC_06 PC_08_Polarity PC_08_mask PC_08 PC_15_Polarity PC_15_mask PC_15 Figure 10 External Interrupt diagram ...

Page 149: ... 3 2 1 0 res res res res res res res res res res res res res res IEN POL R W R W 0 POL External interrupt polarity selection register These bits are written by S W 0 interrupt occurs when pad detect HIGH level signal 1 interrupt occurs when pad detect LOW level signal 1 PA00IEN External interrupt enable register These bits are written by S W 0 external interrupt disable 1 external interrupt enable...

Page 150: ... characteristics of pads are pull up pull down driving strength input enable and CMOS Schmitt trigger input buffer Each pad can be controlled individually by register 17 3 Functional description Figure 11 shows the function schematic of digital I O pad of W7500x Figure 11 function schematic of digital I O pad Figure 12 shows the function schematic of digital analog mux IO pad of W7500x Figure 12 f...

Page 151: ...elect PD Pull down enable User can set pad condition with IE CS PU PD OD DS by register And pads are can be controlled individually Condition A Y P Input buffer enable IE 1 Output mode OUT OUT OUT Input mode No use IN IN Input buffer disable IE 0 Output mode OUT Low 0 OUT Input mode No use IN IN Condition Rise Fall Time nSec Propagation Delay nSec Driving Strength Capacitance loading Min Max Min M...

Page 152: ... down selection register These bits are written by S W 00 Neither 01 pull down 10 pull up 11 Neither 2 DS Driving strength selection register 0 High driving strength 1 Low driving strength 3 OD Open Drain output mode register 0 Open Drain output mode disable 1 Open Drain output mode enable 5 IE Input buffer enable selection register 0 Input buffer disable 1 Input buffer enable 6 CS CMOS input or S...

Page 153: ...ask registers allow treating sets of port bits as a group leaving other bits unchanged Up to 34 GPIOs depending on configuration Programmable control for GPIO interrupts Interrupt generation masking Edge triggered on rising falling or both 18 3 Functional description Figure 13 shows the GPIO block diagram AHB interface Register Block 0 1 0 1 GPIO_DATAOUT GPIO_DATAIN GPIO_SET 15 0 ALTF_SET GPIOINT ...

Page 154: ...mits individual bits or multiple bits to be read from or written to in a single transfer This avoids software based read modify write operations that are not thread safe With the masked access operations the 16 bit I O is divided into two halves lower byte and upper byte The bit mask address spaces are defined as two arrays each containing 256 words For example to set bits 1 0 to 1 and clear bits ...

Page 155: ...a data array of 32 bit x 256 Figure 15 MASK LOWBYTE access To update some of the bits in the upper eight bits of the GPIO port users can use the MASKHIGHBYTE array as Figure 16 below Upper byte masked access register lower byte masked access register 0x0800 0x0400 DATA Control register 0x0000 Address offset DATAOUT 0x322B set bit 12 11 to 0 clear bit 15 to 1 bit mask b1001_1000 0x98 MASK_LOWBYTE 0...

Page 156: ...9 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 DAT15 DAT14 DAT13 DAT12 DAT11 DAT10 DAT9 DAT8 DAT7 DAT6 DAT5 DAT4 DAT3 DAT2 DAT1 DAT0 R R R R R R R R R R R R R R R R 31 30 29 28 27 26 25 24 23 ...

Page 157: ...gister GPIOx_OUTENCLR x A D Address offset 0x0014 Reset value 0x0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 EC15 EC14 EC13 EC12 EC11 EC10 EC9 EC8 EC7 EC6 EC5 EC4 EC3 EC2 EC1 EC0 R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W 15 0 ECy y 0 15 WRITE as 0 is no effect 1 is cl...

Page 158: ...icates the interrupt enable GPIO Interrupt Enable Clear Register GPIOx_ INTENCLR x A D Address offset 0x0024 Reset value 0x 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IEC15 IEC14 IEC13 IEC12 IEC11 IEC10 IEC9 IEC8 IEC7 IEC6 IEC5 IEC4 IEC3 IEC2 IEC1 IEC0 R W R W R W R W R W R W R W R W R W R W ...

Page 159: ...lling edge or rising edge GPIO Interrupt Type Clear Register GPIOx_ INTTYPECLR x A D Address offset 0x002c Reset value 0x 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ITC15 ITC14 ITC13 ITC12 ITC11 ITC10 ITC9 ITC8 ITC7 ITC6 ITC5 ITC4 ITC3 ITC2 ITC1 ITC0 R W R W R W R W R W R W R W R W R W R W R ...

Page 160: ...r LOW level or falling edge 1 is indicates for HIGH level or rising edge GPIO Interrupt Polarity Clear Register GPIOx_ INTPOLCLR x A D Address offset 0x0034 Reset value 0x 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 IPC15 IPC14 IPC13 IPC12 IPC11 IPC10 IPC9 IPC8 IPC7 IPC6 IPC5 IPC4 IPC3 IPC2 IP...

Page 161: ... R W R W R W R W R W R W R W 15 0 ISCy y 0 15 WRITE as 0 is no effect 1 is request to clear the interrupt READ as IRQ status Register GPIO Lower Byte Masked Access Register GPIOx_ LB_MASKED x A D Address offset 0x0400 0x07FC Reset value 0x 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res re...

Page 162: ...4 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 HBM res res res res res res res res R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Higher eight bits masked access 15 8 Data for higher byte access with bits 9 2 of address value used as enable bit mask for each bit 7 0 Not used ...

Page 163: ...W7500x Reference Manual Version1 1 0 163 399 18 5 Register map The following Table 13 summarizes the GPIO registers Table 13 GPIO register map and reset values ...

Page 164: ... the Technical Reference Manual 19 2 Features 6 channels Each channel is connected to dedicated hardware DMA requests and software trigger is also supported on each channel Priorities between requests from the DMA channels are software programmable 2 levels consisting of high default Memory to memory transfer software request only TCP IP to memory transfer software request only SPI UART to memory ...

Page 165: ...he controller uses four bits in the channel control data structure that configures how many AHB bus transfers occur before the controller re arbitrates These bits are known as the R_power bits because the value R is raised to the power of two and this determines the arbitration rate For example if R 4 then the arbitration rate is 24 which means the controller arbitrates every 16 DMA transfers Rema...

Page 166: ...nnel the flow for basic cycle is as below 1 The controller performs 2R transfers If the number of transfers remaining is zero the flow continues at step 3 2 The controller arbitrates If a higher priority channel is requesting service then the controller services that channel If the peripheral or software signals a request to the controller then it continues at step 1 3 The controller sets dma_done...

Page 167: ...one of the data structures and then performs a DMA cycle using the other data structure The controller continues to switch between primary and alternate structures until it reads a data structure that is invalid until the user reprograms the cycle_type to basic or until the host processor disables the channel In ping pong mode the user can program or reprogram one of the two channel data structure...

Page 168: ...W7500x Reference Manual Version1 1 0 168 399 Figure 18 DMA ping pong cycle 19 4 Registers Base address 0x4100_4000 DMA status register DMA_STATUS Address offset 0x000 ...

Page 169: ... These bits are read only register to check current state of controller State can be one of the following 0000 idle 0001 reading channel controller data 0010 reading source data end pointer 0011 reading destination data end pointer 0100 reading source data 0101 writing destination data 0110 waiting channel controller data 1000 stalled 1001 done 1010 peripheral scatter gather transition 1011 1111 u...

Page 170: ...ring DMA control data base pointer register DMA_CTRL_BASE_PTR Address offset 0x008 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CTRL_BASE_PTR 31 16 R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CTRL_BASE_PTR 15 8 res res res res res res res res R W 31 8 CTRL_BASE_PTR Pointer to the base address of the primary data structure These bits are read write register User must config...

Page 171: ...5 0 RO Channel 1 DMA_WAITONREQ Channel wait on request status This read only register returns the status of dma_waitonreq Channel 1 0 dma_waitonreq is low 1 dma_waitonreq is high DMA channel software request register DMA_CHNL_SW_REQUEST Address offset 0x014 Reset value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 ...

Page 172: ...uest dma_sreq Channel 1 input from generating requests and therefore only the request dma_req Channel 1 generates requests Reading the register returns the useburst status Read as 0 DMA Channel 1 responds to requests that it receives on dma_req Channel 1 or dma_sreq Channel 1 1 DMA Channel 1 does not responds to requests that it receives on dma_sreq Channel 1 The controller only responds to dma_re...

Page 173: ...6 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res CHNL_REQ_MASK_SET 5 0 R W Channel 1 CHNL_REQ_MASK_SET Returns the request mask status of dma_req Channel 1 and dma_sreq Channel 1 or disables the corresponding channel from generating DMA requests This read write register disables a HIGH on dma_req Channel...

Page 174: ...sreq Channel 1 0 No effect Use the CHNL_REQ_MASK_SET register to disable dma_req Channel 1 and dma_sreq Channel 1 from generating requests 1 Enables dma_req Channel 1 or dma_sreq Channel to generate DMA requests DMA channel enable set register DMA_CHNL_ENABLE_SET Address offset 0x028 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res...

Page 175: ...L_ENABLE_CLR Set the appropriate bit to disable the corresponding DMA channel This write only register disable a DMA channel 0 No effect Use the CHNL_ENABLE_SET register to enable DMA channel 1 Disable channel Channel 1 DMA channel primary alternate set register DMA_CHNL_PRI_ALT_SET Address offset 0x030 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res...

Page 176: ... 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res CHNL_PRI_ALT_CLR 5 0 WO Channel 1 CHNL_PRI_ALT_CLR Set the appropriate bit to select the primary data structure for the corresponding DMA channel This write only register configures a DMA channels to use the prim...

Page 177: ...e high priority level DMA channel priority clear register DMA_CHNL_PRIORITY_CLR Address offset 0x03C Reset value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res CHNL_PRIORITY_CLR 5 0 WO Channel 1 CHNL_PRIORITY_CLR Set the appropriate bit to select the defaul...

Page 178: ... 3 2 1 0 res res res res res res res res res res res res res res res ERR_CLR R W 0 ERR_CLR Returns the status of DMA_ERR or set the signal LOW This read write register returns the status of DMA_ERR and enables set DMA_ERR LOW Read as 0 DMA_ERR is LOW 1 DMA_ERR is HIGH Write as 0 No effect status of DMA_ERR is unchanged 1 Sets DMA_ERR LOW ...

Page 179: ...s res res res res res res res res res res res res res res res reset value 0 0 0 0 0 0 DMA_CHNL_REQ_MASK_CLR res res res res res res res res res res res res res res res res res res res res res res res res res res reset value DMA_CHNL_ENABLE_SET res res res res res res res res res res res res res res res res res res res res res res res res res res reset value 0 0 0 0 0 0 DMA_CHNL_ENABLE_CLR res res ...

Page 180: ...d in single mode The result of the ADC is stored in 12 bit register 20 2 Features 12bit configuration resolution Conversion time Max 10MHz Sampling time can be programmable 8 channel for external analog inputs CH0 PC_15 CH1 PC_14 CH2 PC_13 CH3 PC_12 CH4 PC_11 CH5 PC_10 CH6 PC_09 CH7 PC_08 1 channel for internal LDO 1 5v voltage CH15 Internal voltage Start of conversion can be initiated by software...

Page 181: ...C block diagram Operation ADC with non interrupt Figure 20 shows the flowchart of ADC operation with non interrupt ADC can be used as below 1 ADC needs to be initialized before operation To initialize the ADC clear the PWD bit first 2 Select the ADC channel from 0 to 7 and 15 initial core voltage 3 Run start ADC conversion by set ADC_SRT bit 4 Check INT bit to know finish of conversion 5 If INT bi...

Page 182: ...1 0 182 399 START ADC Power On PWD 0 Select Channel ADC_CHSEL CHECK INT bit INT 1 Read ADC conversion data ADC_DATA ADC Start ADC_SRT YES NO ADC again ADC Power off PWD 1 NO YES Figure 20 The ADC operation flowchart with non interrupt ...

Page 183: ...know when enabling interrupt mask bit and conversion is completed START ADC Power On PWD 0 Interrupt MASK enable MASK 1 Select Channel ADC_CHSEL ADC Start ADC_SRT Wait until Interrupt occured Read ADC conversion data ADC_DATA ADC again ADC Power off PWD 1 NO YES Figure 21 The ADC operation flowchart with interrupt 20 4 Registers Base address 0x4100_0000 ADC control register ADC_CTR Address offset ...

Page 184: ... enable disable power down mode O Active 1 Power down ADC channel select register ADC_CHSEL Address offset 0x004 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res CHSEL R W 3 0 CHSEL ADC Channel Select These bits are written by ...

Page 185: ...t set by S W to start ADC for conversion This bit is write only 0 ready to start 1 start ADC for conversion This bit clear automatically after conversion ADC conversion data register ADC_DATA Address offset 0x00C Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res r...

Page 186: ...nterrupt mask signal This bit is interrupt mask bit of ADC This bit can be set and cleared by S W to enable disable interrupt mask 0 Interrupt disable 1 Interrupt enable ADC Interrupt Clear register ADC_INTCLR Address offset 0x01c Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2...

Page 187: ...s res res res res res res res res res res reset value 0 0 0 0 ADC_START res res res res res res res res res res res res res res res res res res res res res res res res res res res res res res res START reset value 0 ADC_DATA res res res res res res res res res res res res res res res res res res res res reset value 0 0 0 0 0 0 0 0 0 0 0 0 ADC_INT res res res res res res res res res res res res res...

Page 188: ...can have different or same clock source Counter or timer operation Eight capture registers that can take the timer value when an external input signal A capture event can generate an interrupt signal optionally 32 bit match register and limit register Timer Counter 0 7 Prescale Register 0 7 Prescale Counter 0 7 Match Interrupt Match Register 0 7 Timer Counter control Register 0 7 Limit Register 0 ...

Page 189: ...rnal input signal and generate interrupts when specified timer values are occurred based on match register and limit register The Timer Counter can count up or down The PWM has match registers and limit registers The match registers control the duty cycle of PWM output waveform The limit registers control the period of the PWM output waveform The Timer Counter becomes 0 when it reaches value of th...

Page 190: ...nter restarts if repetition mode is one shot mode the Timer Counter stops Figure 25 shows up count mode timing diagram Figure 25 Up count mode In Down count mode the Timer Counter counts from 0xFFFF_FFFF then recycles If repetition mode is periodic the Timer Counter restarts if repetition mode is one shot mode the Timer Counter stops Figure 26 shows down count mode timing diagram Figure 26 Down co...

Page 191: ... edge and both edge The counter mode has up count or down count mode and also has periodic or one shot mode The external input pin and PWM output pin are the same so PWM output is disabled in counter mode Figure 27 is counter mode example with rising edge mode Figure 28 is with falling edge mode and Figure 29 is with both rising and falling edge mode Figure 27 Counter mode with rising edge Figure ...

Page 192: ...some examples of the Timer Counter timing with prescale register is 2 match register is 2 limit register is 12 timer mode periodic mode up count mode and no interrupt clear Figure 30 Timer Counter timing diagram with match interrupt External Input Timer Counter 2 4 0 Start Stop Register Rising edge detect Falling edge detect 1 3 PWMCLK Start Stop Register Prescale Counter 0 1 2 0 1 2 0 1 2 0 1 2 0...

Page 193: ... the value of limit register In one shot mode the PWM output does not change to 1 but stays 0 and the Timer Counter stops The PWM mode can be selected independently on each channel 0 7 by PWM output enable and external input enable register The external input pin and PWM output pin are the same so external input is disabled in PWM mode Figure 32 is an example of the PWM output waveform when the Ti...

Page 194: ...interrupt of channel Each PWM channel has Channel n Interrupt Enable register CHn_IER The CHn_IER includes three types of interrupt match overflow and capture The match interrupt occurs when the Timer Counter is reached to value of match register The overflow interrupt occurs when the Timer Counter is reached to value of limit register The capture interrupt occurs when external input is entered fo...

Page 195: ...r counts up to value of DZCR During the dead zone time both complementary signals are both 0 Users have to adjust the signal depending on the devices that are connected to the outputs and their characteristics If DZCR is bigger than the limit register main output signal is toggled 0 to1 and then 1 to 0 while 1 PWMCLK and inverted output signal is always 0 Figure 34 shows two complementary PWM outp...

Page 196: ...Register CHn_CR and the capture register is not overwritten until capture interrupt is cleared Figure 36 shows the capture event timing diagram There is no interrupt clear so second capture does not save during second rising edge detection Figure 36 Capture event with no interrupt clear PWMCLK Start Stop Register Dead zone Counter Timer Counter 0 PWM output 3 Dead zone counter register 0 1 2 3 1 2...

Page 197: ...iagram with interrupt clear The second capture is saved at the second rising edge detection because there is interrupt clear Figure 37 Capture event with interrupt clear External Input Timer Counter 12 14 Rising edge detect 11 13 10 Capture Interrupt 10 0 0 0 Capture Interrupt clear 4 4 13 ...

Page 198: ...Hn_MR CHn_LR CHn_UDMR CHn_PDMR Timer or Counter mode CHn_TCMR 1 0 00 Timer mode CHn_TCMR 1 0 01 Rising edge 10 Falling edge 11 both edge Timer Counter PWM output Yes No CHn_PEEER 1 0 10 PWM output enable and external input disable Capture Yes No CHn_PEEER 1 0 01 PWM output disable and external input enable CHn_PEEER 1 0 00 11 PWM output disable and external input disable Capture mode Falling edge ...

Page 199: ...y interrupt clear register 0 Capture interrupt does not occur 1 Capture interrupt occurs Channel 0 interrupt enable register PWMCH0IER Base address 0x4000_5000 Address offset 0x04 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res re...

Page 200: ... Match interrupt is cleared 1 OIC Overflow Interrupt 0 No action 1 Overflow Interrupt is cleared 2 CIC Capture Interrupt Clear 0 No action 1 Capture Interrupt is cleared Channel 0 Timer Counter Register PWMCH0TCR Base address 0x4000_5000 Address offset 0x0C Reset value 0x0000_0000 31 0 TCR R 31 0 TCR Timer Counter register Timer Counter register These register hold the current values of the Timer ...

Page 201: ...es of prescale counter PC The PC is incremented to the value stored in PR When the PC is reached to PR the TC is incremented and the PC is reset as 0 Channel 0 Prescale Register PWMCH0PR Base address 0x4000_5000 Address offset 0x14 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 ...

Page 202: ... 31 0 LR Limit Register Limit Register The LR can generate an overflow interrupt and PWM output waveform becomes 1 when the TC is reached to the LR Match register should be smaller than limit register LR If not match interrupt is not occurred and PWM output waveform is always 1 Channel 0 Up Down Mode Register PWMCH0UDMR Base address 0x4000_5000 Address offset 0x20 Reset value 0x0000_0000 31 30 29 ...

Page 203: ...ter mode with counting driven by falling edge external input 11 Counter mode with counting driven by rising and falling edge external input Channel 0 PWM output Enable and External input Enable Register PWMCH0PEEER Base address 0x4000_5000 Address offset 0x28 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 1...

Page 204: ...r Counter is captured when external input signal is rising edge 1 Timer Counter is captured when external input signal is falling edge Channel 0 Capture Register PWMCH0CR Base address 0x4000_5000 Address offset 0x30 Reset value 0x0000_0000 31 0 CR R 31 0 CR Capture Register Capture register The CR is loaded with the value of the TC when external input signal is triggered Channel 0 Periodic Mode Re...

Page 205: ...Address offset 0x38 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res res DZE R W 0 DZE Dead Zone Enable 0 Dead zone generation is disabled 1 Dead zone generation is enabled Channel 0 Dead Zone Counter Register PWMCH0DZC...

Page 206: ...e Counter value Dead zone generation counter value register If the DZE bit in DZER is 1 dead zone counter counts to this value and during this time the two PWM output waveforms are all 0 21 5 Register map The following Table 17 summarizes the PWM Channel 0 registers ...

Page 207: ... 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PWMCH0UDMR res res res res res res res res res res res res res res res res res res res res res res res res res res res res res res res UDM Channel 0 Up Down Mode Register reset value 0 PWMCH0TCMR res res res res res res res res res res res res res res res res res res res res res res res res res res res res res res Channel 0 Timer Cou...

Page 208: ...er O Match interrupt does not occur 1 Match interrupt occurs 1 OI Overflow Interrupt This bit is set by hardware and cleared by interrupt clear register O Overflow interrupt does not occur 1 Overflow interrupt occurs 2 CI Capture Interrupt This bit is set by hardware and cleared by interrupt clear register O Capture interrupt does not occur 1 Capture interrupt occurs Channel 1 interrupt enable reg...

Page 209: ...08 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res CIC OIC MIC W W W This bit is set by software cleared by hardware when a capture interrupt becomes 0 0 MIC Match Interrupt O No action 1 Match interrupt is cleared 1 OIC Overflow Interrupt O No a...

Page 210: ...100 Address offset 0x10 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res PCR R 5 0 PC Prescale Counter register Prescale Counter register These registers hold the current values of prescale counter PC The PC is incremented to the value...

Page 211: ...atch interrupt and PWM output waveform becomes 0 when the TC is reached to the MR Match register should be smaller than limit register LR If not match interrupt is not occurred and PWM output waveform is always 1 Channel 1 Limit Register PWMCH1LR Base address 0x4000_5100 Address offset 0x1C Reset value 0x0000_0000 31 0 LR R W 31 0 LR Limit Register Limit Register The LR can generate an overflow in...

Page 212: ...unt 1 TC runs down count Channel 1 Timer Counter Mode Register PWMCH1TCMR Base address 0x4000_5100 Address offset 0x24 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res TCM R W 1 0 TCM Timer Counter mode 00 Timer mode 01...

Page 213: ...l input is disable 01 PWM output is disable and external input is enable 10 PWM output is enable and external input is disable Channel 1 Capture Mode Register PWMCH1CMR Base address 0x4000_5100 Address offset 0x2C Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res ...

Page 214: ...0 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res res PDM R W 0 PDM Periodic Mode 0 Periodic mode When the TC is reached to the LR the TC returns to 0 and then continues counting periodically 1 One shot mode When the TC is reached to the LR the TC returns to 0 and then stops counting Channel 1 Dead Zone Enable Register PWMCH1DZER Base address 0x4000_5100 Address offset ...

Page 215: ...offset 0x3C Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res DZC R W 9 0 DZC Dead Zone Counter value Dead zone generation counter value register If the DZE bit in DZER is 1 dead zone counter counts to this value and during this time the two PWM output...

Page 216: ...1LR Channel 1 Limit Register reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PWMCH1UDMR res res res res res res res res res res res res res res res res res res res res res res res res res res res res res res res UDM Channel 1 Up Down Mode Register reset value 0 PWMCH1TCMR res res res res res res res res res res res res res res res res res res res res res res res res res...

Page 217: ...er O Match interrupt does not occur 1 Match interrupt occurs 1 OI Overflow Interrupt This bit is set by hardware and cleared by interrupt clear register O Overflow interrupt does not occur 1 Overflow interrupt occurs 2 CI Capture Interrupt This bit is set by hardware and cleared by interrupt clear register O Capture interrupt does not occur 1 Capture interrupt occurs Channel 2 interrupt enable reg...

Page 218: ...08 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res CIC OIC MIC W W W This bit is set by software cleared by hardware when a capture interrupt becomes 0 0 MIC Match Interrupt O No action 1 Match interrupt is cleared 1 OIC Overflow Interrupt O No a...

Page 219: ...200 Address offset 0x10 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res PCR R 5 0 PC Prescale Counter register Prescale Counter register These registers hold the current values of prescale counter PC The PC is incremented to the value...

Page 220: ...form becomes 0 when the TC is reached to the MR Match register should be smaller than limit register LR If not match interrupt is not occurred and PWM output waveform is always 1 Channel 2 Limit Register PWMCH2LR Base address 0x4000_5200 Address offset 0x1C Reset value 0x0000_0000 31 0 LR R W 31 0 LR Limit Register Limit Register The LR can generate an overflow interrupt and PWM output waveform be...

Page 221: ... offset 0x24 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res TCM R W 1 0 TCM Timer Counter mode 00 Timer mode 01 Counter mode with counting driven by rising edge external input 10 Counter mode with counting driven by f...

Page 222: ...external input is disable Channel 2 Capture Mode Register PWMCH2CMR Base address 0x4000_5200 Address offset 0x2C Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res res CM R W 0 CM Capture mode 0 Timer Counter is captured ...

Page 223: ...s res PDM R W 0 PDM Periodic Mode 0 Periodic mode When the TC is reached to the LR the TC returns to 0 and then continues counting periodically 1 One shot mode When the TC is reached to the LR the TC returns to 0 and then stops counting Channel 2 Dead Zone Enable Register PWMCH2DZER Base address 0x4000_5200 Address offset 0x38 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16...

Page 224: ...8 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res DZC R W 9 0 DZC Dead Zone Counter value Dead zone generation counter value register If the DZE bit in DZER is 1 dead zone counter counts to this value and during this time the two PWM output waveforms are all 0 ...

Page 225: ...2LR Channel 2 Limit Register reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PWMCH2UDMR res res res res res res res res res res res res res res res res res res res res res res res res res res res res res res res UDM Channel 2 Up Down Mode Register reset value 0 PWMCH2TCMR res res res res res res res res res res res res res res res res res res res res res res res res res...

Page 226: ... register O Match interrupt does not occur 1 Match interrupt occurs 1 OI Overflow Interrupt This bit is set by hardware and cleared by interrupt clear register O Overflow interrupt does not occur 1 Overflow interrupt occurs 2 CI Capture Interrupt This bit is set by hardware and cleared by interrupt clear register O Capture interrupt does not occur 1 Capture interrupt occurs Channel 3 interrupt ena...

Page 227: ...set 0x08 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res CIC OIC MIC W W W This bit is set by software cleared by hardware when a capture interrupt becomes 0 0 MIC Match Interrupt O No action 1 Match interrupt is cleared 1 OIC Overflow Interrupt ...

Page 228: ...300 Address offset 0x10 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res PCR R 5 0 PC Prescale Counter register Prescale Counter register These registers hold the current values of prescale counter PC The PC is incremented to the value...

Page 229: ...atch interrupt and PWM output waveform becomes 0 when the TC is reached to the MR Match register should be smaller than limit register LR If not match interrupt is not occurred and PWM output waveform is always 1 Channel 3 Limit Register PWMCH3LR Base address 0x4000_5300 Address offset 0x1C Reset value 0x0000_0000 31 0 LR R W 31 0 LR Limit Register Limit Register The LR can generate an overflow in...

Page 230: ...unt 1 TC runs down count Channel 3 Timer Counter Mode Register PWMCH3TCMR Base address 0x4000_5300 Address offset 0x24 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res TCM R W 1 0 TCM Timer Counter mode 00 Timer mode 01...

Page 231: ...l input is disable 01 PWM output is disable and external input is enable 10 PWM output is enable and external input is disable Channel 3 Capture Mode Register PWMCH3CMR Base address 0x4000_5300 Address offset 0x2C Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res ...

Page 232: ... 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res res PDM R W 0 PDM Periodic Mode 0 Periodic mode When the TC is reached to the LR the TC returns to 0 and then continues counting periodically 1 One shot mode When the TC is reached to the LR the TC returns to 0 and then stops counting Channel 3 Dead Zone Enable Register PWMCH3DZER Base address 0x4000_5300 Address offse...

Page 233: ...s offset 0x3C Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res DZC R W 9 0 DZC Dead Zone Counter value Dead zone generation counter value register If the DZE bit in DZER is 1 dead zone counter counts to this value and during this time the two PWM outp...

Page 234: ...3LR Channel 3 Limit Register reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PWMCH3UDMR res res res res res res res res res res res res res res res res res res res res res res res res res res res res res res res UDM Channel 3 Up Down Mode Register reset value 0 PWMCH3TCMR res res res res res res res res res res res res res res res res res res res res res res res res res...

Page 235: ... register O Match interrupt does not occur 1 Match interrupt occurs 1 OI Overflow Interrupt This bit is set by hardware and cleared by interrupt clear register O Overflow interrupt does not occur 1 Overflow interrupt occurs 2 CI Capture Interrupt This bit is set by hardware and cleared by interrupt clear register O Capture interrupt does not occur 1 Capture interrupt occurs Channel 4 interrupt ena...

Page 236: ...set 0x08 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res CIC OIC MIC W W W This bit is set by software cleared by hardware when a capture interrupt becomes 0 0 MIC Match Interrupt O No action 1 Match interrupt is cleared 1 OIC Overflow Interrupt ...

Page 237: ...0x10 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res PCR R 5 0 PC Prescale Counter register Prescale Counter register These registers hold the current values of prescale counter PC The PC is incremented to the value stored in PR When ...

Page 238: ... reached to the MR Match register should be smaller than limit register LR If not match interrupt is not occurred and PWM output waveform is always 1 Channel 4 Limit Register PWMCH4LR Base address 0x4000_5400 Address offset 0x1C Reset value 0x0000_0000 31 0 LR R W 31 0 LR Limit Register Limit Register The LR can generate an overflow interrupt and PWM output waveform becomes 1 when the TC is reache...

Page 239: ...24 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res TCM R W 1 0 TCM Timer Counter mode 00 Timer mode 01 Counter mode with counting driven by rising edge external input 10 Counter mode with counting driven by falling edg...

Page 240: ...external input is disable Channel 4 Capture Mode Register PWMCH4CMR Base address 0x4000_5400 Address offset 0x2C Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res res CM R W 0 CM Capture mode 0 Timer Counter is captured ...

Page 241: ...s res PDM R W 0 PDM Periodic Mode 0 Periodic mode When the TC is reached to the LR the TC returns to 0 and then continues counting periodically 1 One shot mode When the TC is reached to the LR the TC returns to 0 and then stops counting Channel 4 Dead Zone Enable Register PWMCH4DZER Base address 0x4000_5400 Address offset 0x38 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16...

Page 242: ...8 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res DZC R W 9 0 DZC Dead Zone Counter value Dead zone generation counter value register If the DZE bit in DZER is 1 dead zone counter counts to this value and during this time the two PWM output waveforms are all 0 ...

Page 243: ...4LR Channel 4 Limit Register reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PWMCH4UDMR res res res res res res res res res res res res res res res res res res res res res res res res res res res res res res res UDM Channel 4 Up Down Mode Register reset value 0 PWMCH4TCMR res res res res res res res res res res res res res res res res res res res res res res res res res...

Page 244: ... register O Match interrupt does not occur 1 Match interrupt occurs 1 OI Overflow Interrupt This bit is set by hardware and cleared by interrupt clear register O Overflow interrupt does not occur 1 Overflow interrupt occurs 2 CI Capture Interrupt This bit is set by hardware and cleared by interrupt clear register O Capture interrupt does not occur 1 Capture interrupt occurs Channel 5 interrupt ena...

Page 245: ...set 0x08 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res CIC OIC MIC W W W This bit is set by software cleared by hardware when a capture interrupt becomes 0 0 MIC Match Interrupt O No action 1 Match interrupt is cleared 1 OIC Overflow Interrupt ...

Page 246: ...500 Address offset 0x10 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res PCR R 5 0 PC Prescale Counter register Prescale Counter register These registers hold the current values of prescale counter PC The PC is incremented to the value...

Page 247: ...form becomes 0 when the TC is reached to the MR Match register should be smaller than limit register LR If not match interrupt is not occurred and PWM output waveform is always 1 Channel 5 Limit Register PWMCH5LR Base address 0x4000_5500 Address offset 0x1C Reset value 0x0000_0000 31 0 LR R W 31 0 LR Limit Register Limit Register The LR can generate an overflow interrupt and PWM output waveform be...

Page 248: ... offset 0x24 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res TCM R W 1 0 TCM Timer Counter mode 00 Timer mode 01 Counter mode with counting driven by rising edge external input 10 Counter mode with counting driven by f...

Page 249: ... enable and external input is disable Channel 5 Capture Mode Register PWMCH5CMR Base address 0x4000_5500 Address offset 0x2C Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res res CM R W 0 CM Capture mode 0 Timer Counter ...

Page 250: ...es res res res res PDM R W 0 PDM Periodic Mode 0 Periodic mode When the TC is reached to the LR the TC returns to 0 and then continues counting periodically 1 One shot mode When the TC is reached to the LR the TC returns to 0 and then stops counting Channel 5 Dead Zone Enable Register PWMCH5DZER Base address 0x4000_5500 Address offset 0x38 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 2...

Page 251: ...8 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res DZC R W 9 0 DZC Dead Zone Counter value Dead zone generation counter value register If the DZE bit in DZER is 1 dead zone counter counts to this value and during this time the two PWM output waveforms are all 0 ...

Page 252: ...5LR Channel 5 Limit Register reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PWMCH5UDMR res res res res res res res res res res res res res res res res res res res res res res res res res res res res res res res UDM Channel 5 Up Down Mode Register reset value 0 PWMCH5TCMR res res res res res res res res res res res res res res res res res res res res res res res res res...

Page 253: ... register O Match interrupt does not occur 1 Match interrupt occurs 1 OI Overflow Interrupt This bit is set by hardware and cleared by interrupt clear register O Overflow interrupt does not occur 1 Overflow interrupt occurs 2 CI Capture Interrupt This bit is set by hardware and cleared by interrupt clear register O Capture interrupt does not occur 1 Capture interrupt occurs Channel 6 interrupt ena...

Page 254: ...set 0x08 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res CIC OIC MIC W W W This bit is set by software cleared by hardware when a capture interrupt becomes 0 0 MIC Match Interrupt O No action 1 Match interrupt is cleared 1 OIC Overflow Interrupt ...

Page 255: ...600 Address offset 0x10 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res PCR R 5 0 PC Prescale Counter register Prescale Counter register These registers hold the current values of prescale counter PC The PC is incremented to the value...

Page 256: ...atch interrupt and PWM output waveform becomes 0 when the TC is reached to the MR Match register should be smaller than limit register LR If not match interrupt is not occurred and PWM output waveform is always 1 Channel 6 Limit Register PWMCH6LR Base address 0x4000_5600 Address offset 0x1C Reset value 0x0000_0000 31 0 LR R W 31 0 LR Limit Register Limit Register The LR can generate an overflow in...

Page 257: ...unt 1 TC runs down count Channel 6 Timer Counter Mode Register PWMCH6TCMR Base address 0x4000_5600 Address offset 0x24 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res TCM R W 1 0 TCM Timer Counter mode 00 Timer mode 01...

Page 258: ...l input is disable 01 PWM output is disable and external input is enable 10 PWM output is enable and external input is disable Channel 6 Capture Mode Register PWMCH6CMR Base address 0x4000_5600 Address offset 0x2C Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res ...

Page 259: ... 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res res PDM R W 0 PDM Periodic Mode 0 Periodic mode When the TC is reached to the LR the TC returns to 0 and then continues counting periodically 1 One shot mode When the TC is reached to the LR the TC returns to 0 and then stops counting Channel 6 Dead Zone Enable Register PWMCH6DZER Base address 0x4000_5600 Address offse...

Page 260: ...s offset 0x3C Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res DZC R W 9 0 DZC Dead Zone Counter value Dead zone generation counter value register If the DZE bit in DZER is 1 dead zone counter counts to this value and during this time the two PWM outp...

Page 261: ...6LR Channel 6 Limit Register reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PWMCH6UDMR res res res res res res res res res res res res res res res res res res res res res res res res res res res res res res res UDM Channel 6 Up Down Mode Register reset value 0 PWMCH6TCMR res res res res res res res res res res res res res res res res res res res res res res res res res...

Page 262: ... register O Match interrupt does not occur 1 Match interrupt occurs 1 OI Overflow Interrupt This bit is set by hardware and cleared by interrupt clear register O Overflow interrupt does not occur 1 Overflow interrupt occurs 2 CI Capture Interrupt This bit is set by hardware and cleared by interrupt clear register O Capture interrupt does not occur 1 Capture interrupt occurs Channel 7 interrupt ena...

Page 263: ...set 0x08 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res CIC OIC MIC W W W This bit is set by software cleared by hardware when a capture interrupt becomes 0 0 MIC Match Interrupt O No action 1 Match interrupt is cleared 1 OIC Overflow Interrupt ...

Page 264: ...700 Address offset 0x10 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res PCR R 5 0 PC Prescale Counter register Prescale Counter register These registers hold the current values of prescale counter PC The PC is incremented to the value...

Page 265: ...atch interrupt and PWM output waveform becomes 0 when the TC is reached to the MR Match register should be smaller than limit register LR If not match interrupt is not occurred and PWM output waveform is always 1 Channel 7 Limit Register PWMCH7LR Base address 0x4000_5700 Address offset 0x1C Reset value 0x0000_0000 31 0 LR R W 31 0 LR Limit Register Limit Register The LR can generate an overflow in...

Page 266: ...unt 1 TC runs down count Channel 7 Timer Counter Mode Register PWMCH7TCMR Base address 0x4000_5700 Address offset 0x24 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res TCM R W 1 0 TCM Timer Counter mode 00 Timer mode 01...

Page 267: ...l input is disable 01 PWM output is disable and external input is enable 10 PWM output is enable and external input is disable Channel 7 Capture Mode Register PWMCH7CMR Base address 0x4000_5700 Address offset 0x2C Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res ...

Page 268: ... 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res res PDM R W 0 PDM Periodic Mode 0 Periodic mode When the TC is reached to the LR the TC returns to 0 and then continues counting periodically 1 One shot mode When the TC is reached to the LR the TC returns to 0 and then stops counting Channel 7 Dead Zone Enable Register PWMCH7DZER Base address 0x4000_5700 Address offse...

Page 269: ...s offset 0x3C Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res DZC R W 9 0 DZC Dead Zone Counter value Dead zone generation counter value register If the DZE bit in DZER is 1 dead zone counter counts to this value and during this time the two PWM outp...

Page 270: ...7LR Channel 7 Limit Register reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 PWMCH7UDMR res res res res res res res res res res res res res res res res res res res res res res res res res res res res res res res UDM Channel 7 Up Down Mode Register reset value 0 PWMCH7TCMR res res res res res res res res res res res res res res res res res res res res res res res res res...

Page 271: ... interrupt is enabled 1 IE1 Channel 1 Interrupt Enable 0 Channel 1 interrupt is disabled 1 Channel 1 interrupt is enabled 2 IE2 Channel 2 Interrupt Enable 0 Channel 2 interrupt is disabled 1 Channel 2 interrupt is enabled 3 IE3 Channel 3 Interrupt Enable 0 Channel 3 interrupt is disabled 1 Channel 3 interrupt is enabled 4 IE4 Channel 4 Interrupt Enable 0 Channel 4 interrupt is disabled 1 Channel 4...

Page 272: ...nter stop 1 Timer Counter start 1 SS1 Channel 1 Timer Counter Start or Stop 0 Timer Counter stop 1 Timer Counter start 2 SS2 Channel 2 Timer Counter Start or Stop 0 Timer Counter stop 1 Timer Counter start 3 SS3 Channel 3 Timer Counter Start or Stop 0 Timer Counter stop 1 Timer Counter start 4 SS4 Channel 4 Timer Counter Start or Stop 0 Timer Counter stop 1 Timer Counter start 5 SS5 Channel 5 Time...

Page 273: ...mer Counter is not paused 1 Timer Counter is paused 1 PS1 Channel 1 Timer Counter Pause 0 Timer Counter is not paused 1 Timer Counter is paused 2 PS2 Channel 2 Timer Counter Pause 0 Timer Counter is not paused 1 Timer Counter is paused 3 PS3 Channel 3 Timer Counter Pause 0 Timer Counter is not paused 1 Timer Counter is paused 4 PS0 Channel 4 Timer Counter Pause 0 Timer Counter is not paused 1 Time...

Page 274: ...s res res res res res res res res res res res res res res res IE7 IE6 IE5 IE4 IE3 IE2 IE1 IE0 Interrupt enable register reset value 0 0 0 0 0 0 0 0 SSR res res res res res res res res res res res res res res res res res res res res res res res res SS7 SS6 SS5 SS4 SS3 SS2 SS1 SS0 Start Stop register reset value 0 0 0 0 0 0 0 0 PSR res res res res res res res res res res res res res res res res res ...

Page 275: ...ne set so two FRCs has one clock reset and interrupt but each FRC has an individual clock enable 22 2 Features One dual timer has two Free Running Counters FRCs One dual timer has one interrupt handler and one clock One dual timer has two clock enable signals There are 2 dual timers A 32 bit or a 16 bit down counter One of the following repetition modes one shot and wrapping mode One of the follow...

Page 276: ...as 16 bit or 32 bit using the control register Prescaler The timer has a prescaler that can divide down the enabled clock rate by 1 16 or 256 Repetition mode There are two repetition mode one shot and wrapping mode Wrapping mode has two modes free running and periodic mode One shot mode The counter generates an interrupt once When the counter reaches 0 it halts until users reprogram it Users can d...

Page 277: ...tical The timer is loaded by writing to the load register and counts down to 0 if enabled When a counter is already running writing to the load register causes the counter to immediately restart at the new value Writing to the background load value has no effect on the current count In periodic mode the counter continues to decrease to 0 and restart from the new load value An interrupt is generate...

Page 278: ...t TimerControl 1 1 Prescale 1 16 or 256 1 TimerControl 3 2 0 16 TimerControl 3 2 1 256 TimerControl 3 2 2 Interrupt enable or disable Disable TimerControl 5 0 Ensable TimerControl 5 1 Repetition mode Wrapping or one shot One shot mode TimerControl 0 1 One shot count mode Wrapping mode Free running or Periodic mode Wrapping mode TimerControl 0 0 TimerControl 0 1 Periodic mode Free running mode Time...

Page 279: ...nd the current count reaches 0 Timer0_0 Value Register DUALTIMER0_0TimerValue Base address 0x4000_1000 Address offset 0x04 Reset value 0xFFFF_FFFF 31 0 TVR R 31 0 TVR Timer Value Register This register provides the current value of the decrementing counter Timer0_0 Control Register DUALTIMER0_0TimerControl Base address 0x4000_1000 Address offset 0x08 Reset value 0x0000_0020 31 30 29 28 27 26 25 24...

Page 280: ...imer Mode 0 Timer is in free running mode default 1 Timer is in periodic mode 7 TE Timer Enable 0 Timer disabled default 1 Timer enabled Timer0_0 Interrupt Clear Register DUALTIMER0_0TimerIntClr Base address 0x4000_1000 Address offset 0x0C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res re...

Page 281: ...sked Interrupt Status Register DUALTIMER0_0TimerMIS Base address 0x4000_1000 Address offset 0x14 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res MIS R 0 MIS Masked Interrupt Status Register This register indicates the ...

Page 282: ...alue used to reload the counter when Periodic mode is enabled and the current count reaches 0 This register provides an alternative method of accessing the TimerLoad Register The difference is that writes to TimerBGLoad Register do not cause the counter to immediately restart from the new value Reading from this register returns the same value returned from TimerLoad Register ...

Page 283: ...S OC Timer0_0 Control Register reset value 0 0 1 0 0 0 0 DUALTIMER0_0TimerIntClr res res res res res res res res res res res res res res res res res res res res res res res res res res res res res res res TIC Timer0_0 Interrupt Clear Register reset value Write only register DUALTIMER0_0TimerRIS res res res res res res res res res res res res res res res res res res res res res res res res res res ...

Page 284: ...nd the current count reaches 0 Timer0_1 Value Register DUALTIMER0_1TimerValue Base address 0x4000_1020 Address offset 0x04 Reset value 0xFFFF_FFFF 31 0 TVR R 31 0 TVR Timer Value Register This register provides the current value of the decrementing counter Timer0_1 Control Register DUALTIMER0_1TimerControl Base address 0x4000_1020 Address offset 0x08 Reset value 0x0000_0020 31 30 29 28 27 26 25 24...

Page 285: ...imer is in free running mode default 1 Timer is in periodic mode 7 TE Timer Enable 0 Timer disabled default 1 Timer enabled Timer0_1 Interrupt Clear Register DUALTIMER0_1TimerIntClr Base address 0x4000_1020 Address offset 0x0C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res...

Page 286: ...atus Register DUALTIMER0_1TimerMIS Base address 0x4000_1020 Address offset 0x14 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res MIS R 0 MIS Masked Interrupt Status Register This register indicates the masked interrupt ...

Page 287: ... used to reload the counter when Periodic mode is enabled and the current count reaches 0 This register provides an alternative method of accessing the TimerLoad Register The difference is that writes to TimerBGLoad Register do not cause the counter to immediately restart from the new value Reading from this register returns the same value returned from TimerLoad Register ...

Page 288: ...S OC Timer0_1 Control Register reset value 0 0 1 0 0 0 0 DUALTIMER0_1TimerIntClr res res res res res res res res res res res res res res res res res res res res res res res res res res res res res res res TIC Timer0_1 Interrupt Clear Register reset value Write only register DUALTIMER0_1TimerRIS res res res res res res res res res res res res res res res res res res res res res res res res res res ...

Page 289: ...14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res CE R W 0 CE Clock Enable Register 0 Clock disable 1 Clock enable Timer0_1 Clock Enable Register TIMCLKEN0_1 Base address 0x4000_1080 Address offset 0x20 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 ...

Page 290: ...21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 비고 TIMCLKEN0_0 res res res res res res res res res res res res res res res res res res res res res res res res res res res res res res res CE Timer0_0 Clock Enable Register reset value 0 TIMCLKEN0_1 res res res res res res res res res res res res res res res res res res res res res res res res res res res res res res res CE Timer0_1 Clock Ena...

Page 291: ...rrent count reaches 0 Timer1_0 Value Register DUALTIMER1_0TimerValue Base address 0x4000_2000 Address offset 0x04 Reset value 0xFFFF_FFFF 31 0 TVR R 31 0 TVR Timer Value Register This register provides the current value of the decrementing counter Timer1_0 Control Register DUALTIMER1_0TimerControl Base address 0x4000_2000 Address offset 0x08 Reset value 0x0000_0020 31 30 29 28 27 26 25 24 23 22 21...

Page 292: ...lt 1 Timer is in periodic mode 7 TE Timer Enable 0 Timer disabled default 1 Timer enabled Timer1_0 Interrupt Clear Register DUALTIMER1_0TimerIntClr Base address 0x4000_2000 Address offset 0x0C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res r...

Page 293: ...ress 0x4000_2000 Address offset 0x14 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res MIS R 0 MIS Masked Interrupt Status Register This register indicates the masked interrupt status from the counter This value is the l...

Page 294: ... counter when Periodic mode is enabled and the current count reaches 0 This register provides an alternative method of accessing the TimerLoad Register The difference is that writes to TimerBGLoad Register do not cause the counter to immediately restart from the new value Reading from this register returns the same value returned from TimerLoad Register ...

Page 295: ...TS OC Timer1_0 Control Register reset value 0 0 1 0 0 0 0 DUALTIMER1_0TimerIntClr res res res res res res res res res res res res res res res res res res res res res res res res res res res res res res res TIC Timer1_0 Interrupt Clear Register reset value Write only register DUALTIMER1_0TimerRIS res res res res res res res res res res res res res res res res res res res res res res res res res res...

Page 296: ...rrent count reaches 0 Timer1_1 Value Register DUALTIMER1_1TimerValue Base address 0x4000_2020 Address offset 0x04 Reset value 0xFFFF_FFFF 31 0 TVR R 31 0 TVR Timer Value Register This register provides the current value of the decrementing counter Timer1_1 Control Register DUALTIMER1_1TimerControl Base address 0x4000_2020 Address offset 0x08 Reset value 0x0000_0020 31 30 29 28 27 26 25 24 23 22 21...

Page 297: ...lt 1 Timer is in periodic mode 7 TE Timer Enable 0 Timer disabled default 1 Timer enabled Timer1_1 Interrupt Clear Register DUALTIMER1_1TimerIntClr Base address 0x4000_2020 Address offset 0x0C 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res r...

Page 298: ...R1_1TimerMIS Base address 0x4000_2020 Address offset 0x14 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res MIS R 0 MIS Masked Interrupt Status Register This register indicates the masked interrupt status from the counte...

Page 299: ...ue used to reload the counter when Periodic mode is enabled and the current count reaches 0 This register provides an alternative method of accessing the TimerLoad Register The difference is that writes to TimerBGLoad Register do not cause the counter to immediately restart from the new value Reading from this register returns the same value returned from TimerLoad Register ...

Page 300: ...TS OC Timer1_1 Control Register reset value 0 0 1 0 0 0 0 DUALTIMER1_1TimerIntClr res res res res res res res res res res res res res res res res res res res res res res res res res res res res res res res TIC Timer1_1 Interrupt Clear Register reset value Write only register DUALTIMER1_1TimerRIS res res res res res res res res res res res res res res res res res res res res res res res res res res...

Page 301: ... 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res CE R W 0 CE Clock Enable Register 0 Clock disable 1 Clock enable Timer1_1 Clock Enable Register TIMCLKEN1_1 Base address 0x4000_2080 Address offset 0x20 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9...

Page 302: ...aches 0 The watchdog applies a reset to a system in the event of a software failure to provide a way to recover from software crashes Users can enable or disable the watchdog unit as required 23 2 Features 32 bit down counter Internally resets chip if not periodically reloaded The watchdog timer has lock register to prevent rogue software from disabling the watchdog timer functionality The watchdo...

Page 303: ...terrupt status after masking Figure 41 Watchdog timer operation flow diagram 23 4 Watchdog timer Registers Base address 0x4000_0000 Watchdog timer Load Register WDTLoad Address offset 0x000 Reset value 0xFFFF_FFFF 31 0 WLR R W 31 0 WLR Watchdog timer Load Register This register contains the value from which the counter is to decrement When this register is written to the count is immediately resta...

Page 304: ...2 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res REN IEN R W R W 0 IEN Interrupt Enable 0 Disable the counter and the interrupt 1 Enable the counter and the interrupt Reloads the counter from the value in WDTLoad after previously being disabled 1 REN Reset Request Enable 0 Disable watchdog reset output 1 Enable watchdog reset output Watchdog timer Interrupt Clear...

Page 305: ...t status from the counter This value is ANDed with the interrupt enable bit from the control register to create the masked interrupt that is passed to the interrupt output pin Watchdog timer Masked Interrupt Status Register WDTMIS Address offset 0x014 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 ...

Page 306: ...tionality Writing a value of 0x1ACCE551 enables write access to all other registers Writing any other value disables write accesses A read from this register returns only the bottom bit 0 WES Register Write Enable status 0 Indicates that write access is enabled not locked Default 1 Indicates that write access is disabled locked 31 1 ERW Enable Register Writes Enable write access to all other regis...

Page 307: ...er Value Register reset value 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 WDTControl res res res res res res res res res res res res res res res res res res res res res res res res res res res res res res REN IEN Watchdog timer Control Register reset value 0 0 WDTIntClr res res res res res res res res res res res res res res res res res res res res res res res res res res res r...

Page 308: ...ppropriate Interrupt Set Enable register There are following Counter Interrupts Second Minute Hour Day Day of Week Date Day of Month and Year Each bit of RTCINTM Interrupt Mask Register can disable or enable interrupt for each Counter Interrupt Alarm Interrupt can be generated when the Alarm matches with Counter RTC Counter and Calendar When user writes 1 to bit 0 of control register then the RTC ...

Page 309: ...g flow for Counter Function Figure 48 shows RTC setting flow for Alarm function Figure 43 RTC setting flow for Counter Function Initialize RTC module Enable RTC Wait for RTC clock stabilization time Select 32768Hz oscillator clock for RTC Set Current Time for RTC Enable RTC Counter Interrupt Enable RTC Interrupt and Start Enable NVIC ...

Page 310: ...Changed by a Reset Software must initialize these registers between power on and setting the RTC into operation RTC control register RTCCON Address offset 0x0000 Reset value 0x0000_0000 Initialize RTC module Enable RTC Wait for RTC clock stabilization time Select 32768Hz oscillator clock for RTC Set Current Time for RTC Set Alarm Time Enable RTC Alarm Interrupt Enable RTC Interrupt and Start Enabl...

Page 311: ...d remain reset until RTCCON 1 is changed to 0 5 INTEN RTC Interrupt Enable This bit set and cleared by S W to enable or disable RTC interrupt 0 RTC Interrupt is disabled 1 RTC Interrupt is enabled RTC Interrupt Mask register RTCINTE Address offset 0x0004 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 ...

Page 312: ...enerates an interrupt 3 IMDATE RTC Date Interrupt Enable This bit set and cleared by S W to enable or disable RTC Date interrupt 0 No effect 1 an increment of the Date value generates an interrupt 4 IMDAY RTC Day Interrupt Enable This bit set and cleared by S W to enable or disable RTC Day interrupt 0 No effect 1 an increment of the Day value generates an interrupt 5 IMMON RTC Month Interrupt Enab...

Page 313: ... res res res res res res res res res res RTC ALF RTC CIF R W R W Bit 0 RTCCIF RTC Counter Interrupt pending flag When one the Counter Increment Interrupt block generated an interrupt Writing a one to this bit clears the counter increment interrupt Read 0 No effect Read 1 an increment of the Second value generates an interrupt Write 0 No effect Write 1 clear interrupt Bit 1 RTCALF RTC Alarm interru...

Page 314: ...ared to the Predetermining Minute for the alarm 2 AMRHOUR RTC Alarm Mask for Hour This bit set and cleared by S W to enable or disable comparison for Minute 0 No effect 1 the Hour value is compared to the Predetermining Hour for the alarm 3 AMRDAY RTC Alarm Mask for Day This bit set and cleared by S W to enable or disable comparison for Day of Week 0 No effect 1 the Day value is compared to the Pr...

Page 315: ...s value 0 to 59 RTC BCD Minute register BCDMIN Address offset 0x0014 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res BCDMIN R W R W R W R W R W R W R W Bit 6 0 BCDMIN RTC Minute value 0 to 59 RTC BCD Hour register BCDHOUR Address offset 0...

Page 316: ...egister BCDDATE Address offset 0x0020 Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res BCDDATE R W R W R W R W R W R W Bit 5 0 BCDDATE RTC Day of Month value 1 to 28 29 30 or 31 RTC BCD Month register BCDMON Address offset 0x0024 Reset...

Page 317: ...et 0x002C Reset value 0xXXXX_XXXX NC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res PRESEC R W R W R W R W R W R W R W Bit 6 0 PRESEC RTC PREDETERMINING Seconds value 0 to 59 RTC Predetermining Minute register PREMIN Address offset 0x0030 Reset value 0xXXXX_XXX...

Page 318: ...ue 0xXXXX_XXXX NC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res PREDAY R W R W R W R W Bit 3 0 PREDAY RTC Predetermining Day of Week value 1 to 7 RTC Predetermining Date register PREDATE Address offset 0x003C Reset value 0xXXXX_XXXX NC 31 30 29 28 ...

Page 319: ...xXXXX_XXXX NC 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PREYEAR R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W R W Bit 15 0 PREYEAR RTC Predetermining Year value 0 to 4095 RTC Consolidated Time0 register RTCTIME0 Address offset 0x0048 Reset value 0x0000_0000 31 30 29 28 27 26 25...

Page 320: ...s offset 0x004C Reset value 0x0000_0000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 CBCDYEAR R R R R R R R R R R R R R R R R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res CBCDMON res res CBCDDATE R R R R R R R R R R R Bit 5 0 CBCDDATE RTC Consolidated Day of Month value 1 to 28 29 30 or 31 Bit 12 8 CBCDMON RTC Consolidated Month value 1 to 12 Bit 31 16 CBCDYEAR RTC Consolidated Year value ...

Page 321: ... register reset value 0 0 RTCAMR AMRYEAR AMRMON AMRDATE AMRDAY AMRHOUR AMRMIN AMRSEC Alarm Mask register reset value 0 0 0 0 0 0 0 BCDSEC BCD Second register reset value 0 0 0 0 0 0 0 BCDMIN BCD Minute register reset value 0 0 0 0 0 0 0 BCDHOUR BCD Hour register reset value 0 0 0 0 0 0 0x04 0x08 0x0C 0x10 0x00 BCDSEC BCDMIN BCDHOUR BCDDAY 0x14 0x18 0x1C BCDDAY BCD Day register reset value 0 0 0 0 ...

Page 322: ...19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Note PRESEC Predetermining Second register reset value nc nc nc nc nc nc nc PREMIN Predetermining Minute register reset value nc nc nc nc nc nc nc PREHOUR Predetermining Hour register reset value nc nc nc nc nc nc PRESEC PREMIN 0x2C 0x30 PREHOUR 0x38 PREDAY 0x34 PREDAY Predetermining Day register reset value nc nc nc nc PREDATE Predetermining Date ...

Page 323: ...ister UART1_IBRD UART1_FBRD Figure 45 UART0 1 Block diagram Figure 46 shows the UART character frame UART FIFO status and Interrupt UARTn Interrupt Interrupt Control Status UARTTXINTR APB interface Register Block 32x8 transmit FIFO 32x12 receive FIFO Transmitter Receiver UARTRXINTR UARTMSINTR UARTRTINTR UARTEINTR UARTINTR nUARTRI nUARTCTS nUARTDSR nUARTDCD nUARTDTR nUARTRTS nUARTOut1 nUARTOut2 UAR...

Page 324: ...W7500x Reference Manual Version1 1 0 324 399 Figure 46 UART character frame ...

Page 325: ...the baud rate generator to determine the bit period Baud Rate Divisor UARTCLK 16 𝑏𝑎𝑢𝑑 𝑟𝑎𝑡𝑒 𝐵𝑅𝐷𝐼 𝐵𝑅𝐷𝐹 Figure 47 UART divider flow chart Figure 48 show how to set the UART Initial value Figure 48 UART Initial setting flow chart DL PCLK 16 BR UARTxIBRD Dlinteger UARTxFBRD DLfloat DLinteger 64 0 5 END Calculating UART baudrate BR PCLK BR Initial setting Start Set UARTxLCR_H Word length Stop bit Parity...

Page 326: ...hich means the FIFO is not empty and remains as 1 while data is being transmitted Data receive Received data is stored in the 32 byte FIFOs When a start bit has been received it begins running and data is sampled on the eighth cycle of that counter in UART mode A valid stop bit is confirmed if UARTRXD is 1 When a full word is received the data is stored in the receive FIFO Error bit is stored in b...

Page 327: ... of nUARTRTS signals to the sending UART to continue transmitting data The CTS flow control is enabled the transmitter can only transmit data when nUARTCTS is asserted When nUARTCTR is re asserted to a low the transmitter sends the next byte To stop the transmitter from sending the following byte nUARTCTS must be released before the middle of the last stop bit that is currently being sent Figure 5...

Page 328: ...4 UART0 Registers Base address 0x4000_C000 UART0DR UART0 Data Register Address offset 0x000 Reset value 0x0000_0000 The UART0DR is the data register Initial setting Set RTS CTS of UARTxCR Set FEN of UARTxLCR_H Set RxSel TxSel of UARTxIFLS RXFE of UARTxFR 0 CTS of UARTxFR 0 BUSY of UARTxFR 1 TX RX Yes Yes No No END Send Tx data Yes receive Rx data No ...

Page 329: ...dition was detected indicating that the received data input was held LOW of longer than a full word transmission time defined as start data parity and stop bits 9 PE Parity error 1 it indicates that the parity of the received it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the line control register UARTLCR_H 8 FE Framing error 1 it...

Page 330: ...CR 0 FE Framing error When set to 1 in indicates that the received character didn t have a valid stop bit This bit is cleared to 0 by a write to UART0ECR UART0FR UART0 Flag Register Address offset 0x0018 Reset value 0bx11000xxx 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res re...

Page 331: ...ART busy 1 the UART is busy transmitting data 2 DCD Data carrier detect This bit is the complement of the UART data carrier detect UART0DCD status input 1 The bit is the complement of the UART data carrier detect 1 DSR Data set ready This bit is the complement of the UART data set ready UART0DSR status input 1 The bit is the complement of the UART data set ready 0 CTS Clear to send This bit is the...

Page 332: ...2 11 10 9 8 7 6 5 4 3 2 1 0 BAUD DIVINT w 15 0 BAUD DIVINT The integer baud rate divisor These bits are cleared to 0 on reset UART0FBRD UART0 Fractional Baud Rate Register Address offset 0x0028 Reset value 0x00 The UART0FBRD register is the fractional part of the baud rate divisor value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res ...

Page 333: ...r divisor Fractional divisor Required bit rate bps Generated bit rate bps Error 0x2 0x0B 230400 2 171875 0 07994 0x4 0x16 115200 4 34375 0 07994 0x6 0x21 76800 6 515625 0 07994 0x8 0x2C 57600 8 6875 0 07994 0x22 0x2E 14400 34 71875 0 010001 UART0LCR_H UART0 Line Control Register Address offset 0x002C Reset value 0x00 The UART0LCR_H register is the line control register This register accesses bits ...

Page 334: ...PEN Parity enable 0 parity is disabled and no parity bit added to the data frame 1 parity checking and generations is enabled 0 BRK Send break 0 For normal use the bit must be cleared to 0 1 The low level is continually output on the UARTTXD output PEN EPS SPS Parity bit Transmitted or checked 0 X X Not transmitted or checked 1 1 0 Even parity 1 0 0 Odd parity 1 0 1 1 1 1 1 0 UART0CR UART0 Control...

Page 335: ...o send UART0RTS modem status output That is when the bit is programmed to 1 then UART0RTS is LOW 10 DTS Data transmit ready This bit is the complement of the UART data transmit ready UART0DTR modem status output That is when the bit is programmed to 1 then UART0DTR is LOW 9 RXE Receive enable If this bit is set to 1 the receive section of the UART is enabled Data reception occurs for either UART s...

Page 336: ...ct register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res RXIFLSEL TXIFLSEL W W 5 3 RXIFLSEL Receive interrupt FIFO level select 7 6 5 4 3 2 1 0 Reserved 7 8 full 3 4 full 1 2 full 1 4 full 1 8 full 2 0 TXIFLSEL Transmit interrupt FIFO level select 7 6 5 4...

Page 337: ... UART0OEINTR 1 Enable UART0OEINTR 9 BEIM Break error interrupt mask 0 Disable UART0BEINTR 1 Enable UART0BEINTR 8 PEIM Parity error interrupt mask 0 Disable UART0EINTR 1 Enable UART0EINTR 7 FEIM Framing error interrupt mask 0 Disable UART0FEINTR 1 Enable UART0FEINTR 6 RTIM Receive timeout interrupt mask 0 Disable UART0RTINTR 1 Enable UART0RTINTR 5 TXIM Transmit interrupt mask 0 Disable UART0TXINTR ...

Page 338: ...us It indicates state of the UART0OEINTR interrupt 9 BERIS Break error interrupt status It indicates state of the UART0BEINTR interrupt 8 PERIS Parity error interrupt status It indicates state of the UART0PEINTR interrupt 7 FERIS Framing error interrupt status It indicates state of the UART0FEINTR interrupt 6 RTRIS Receive timeout interrupt status It indicates state of the UART0RTINTR interrupt 5 ...

Page 339: ...It indicates state of the UART0BEINTR interrupt 8 PEMIS Parity error masked interrupt status It indicates state of the UART0PEINTR interrupt 7 FEMIS Framing error masked interrupt status It indicates state of the UART0FEINTR interrupt 6 RTMIS Receive timeout masked interrupt status It indicates state of the UART0RTINTR interrupt 5 TXMIS Transmit masked interrupt status It indicates state of the UA...

Page 340: ...TR interrupt 9 BEIC Break error interrupt clear Clear the UART0BEINTR interrupt 8 PEIC Parity error interrupt clear Clear the UART0PEINTR interrupt 7 FEIC Framing error interrupt clear Clear the UART0FEINTR interrupt 6 RTIC Receive timeout interrupt clear Clear the UART0RTINTR interrupt 5 TXIC Transmit interrupt clear Clear the UART0TXINTR interrupt 4 RXIC Receive interrupt clear Clear the UART0RX...

Page 341: ... res res res res res res res res res res res res res res res res res res SPS FEN STP2 EPS PEN BRK Line Control Register reset value 1 1 1 1 1 1 1 1 0x030 UART0CR res res res res res res res res res res res res res res res res CTSEn RTSEn Out2 out1 RTS DTR RXE TXE res res res res res SIRLP SIREN UART0EN Control Register reset value 0 0 1 1 0 0 0 0 0 0 0 0x034 UART0IFLS res res res res res res res r...

Page 342: ...13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res OE BE PE FE DATA R R R R R W 11 OE Overrun error 0 data is empty 1 data is received and the receive FIFO is already full 10 BE Break error 1 if a break condition was detected indicating that the received data input was held LOW of longer than a full word transmission time defined as start data parity and stop bits 9 PE Parity error 1 it indicates tha...

Page 343: ... PE Parity error When set to 1 it indicates that the parity of the received data character does not match the parity that the EPS and SPS bits in the line control register UARTLCR_H select This bit is cleared to 0 by a write to UART1ECR 0 FE Framing error When set to 1 in indicates that the received character didn t have a valid stop bit This bit is cleared to 0 by a write to UART1ECR UART1FR UART...

Page 344: ...ter UARTLCR_H 0 The bit is set when the receive holding register is empty 1 The bit is set when the receive FIFO is empty 3 BUSY UART busy 1 the UART is busy transmitting data 2 DCD Data carrier detect This bit is the complement of the UART data carrier detect UART1DCD status input 1 The bit is the complement of the UART data carrier detect 1 DSR Data set ready This bit is the complement of the UA...

Page 345: ...3 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BAUD DIVINT w 15 0 BAUD DIVINT The integer baud rate divisor These bits are cleared to 0 on reset UART1FBRD UART1 Fractional Baud Rate Register Address offset 0x0028 Reset value 0x00 The UART1FBRD register is the fractional part of the baud rate divisor value 31 30 29 28 27 ...

Page 346: ...ted baud rate 8 106 16 4 34375 115107 914 Error 115108 115200 115200 100 0 07861 When UartCLK 8MHz Integer divisor Fractional divisor Required bit rate bps Generated bit rate bps Error 0x2 0x0B 230400 2 171875 0 07994 0x4 0x16 115200 4 34375 0 07994 0x6 0x21 76800 6 515625 0 07994 0x8 0x2C 57600 8 6875 0 07994 0x22 0x2E 14400 34 71875 0 010001 UART1LCR_H UART1 Line Control Register Address offset ...

Page 347: ... frame 2 EPS Even parity select 0 odd parity 1 even parity 1 PEN Parity enable 0 parity is disabled and no parity bit added to the data frame 1 parity checking and generations is enabled 0 BRK Send break 0 For normal use the bit must be cleared to 0 1 The low level is continually output on the UARTTXD output PEN EPS SPS Parity bit Transmitted or checked 0 X X Not transmitted or checked 1 1 0 Even ...

Page 348: ...t to send This bit is the complement of the UART request to send UART1RTS modem status output That is when the bit is programmed to 1 then UART1RTS is LOW 10 DTS Data transmit ready This bit is the complement of the UART data transmit ready UART1DTR modem status output That is when the bit is programmed to 1 then UART1DTR is LOW 9 RXE Receive enable If this bit is set to 1 the receive section of t...

Page 349: ...t FIFO Level Select Register Address offset 0x0034 Reset value 0x12 The UARTIFLS register is the interrupt FIFO level select register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res RXIFLSEL TXIFLSEL W W 5 3 RXIFLSEL Receive interrupt FIFO level select 7 6 5...

Page 350: ...R MIM DCD MIM CTS MIM RIMI M R W R W R W R W R W R W R W R W R W R W R W 10 OEIM Overrun error interrupt mask 0 Disable UART1OEINTR 1 Enable UART1OEINTR 9 BEIM Break error interrupt mask 0 Disable UART1BEINTR 1 Enable UART1BEINTR 8 PEIM Parity error interrupt mask 0 Disable UART1EINTR 1 Enable UART1EINTR 7 FEIM Framing error interrupt mask 0 Disable UART1FEINTR 1 Enable UART1FEINTR 6 RTIM Receive ...

Page 351: ... CTSR MIS RI RMIS R R R R R R R R R R R 10 OERIS Overrun error interrupt status It indicates state of the UART1OEINTR interrupt 9 BERIS Break error interrupt status It indicates state of the UART1BEINTR interrupt 8 PERIS Parity error interrupt status It indicates state of the UART1PEINTR interrupt 7 FERIS Framing error interrupt status It indicates state of the UART1FEINTR interrupt 6 RTRIS Receiv...

Page 352: ...the UART1OEINTR interrupt 9 BEMIS Break error masked interrupt status It indicates state of the UART1BEINTR interrupt 8 PEMIS Parity error masked interrupt status It indicates state of the UART1PEINTR interrupt 7 FEMIS Framing error masked interrupt status It indicates state of the UART1FEINTR interrupt 6 RTMIS Receive timeout masked interrupt status It indicates state of the UART1RTINTR interrupt...

Page 353: ...lear Clear the UART1OEINTR interrupt 9 BEIC Break error interrupt clear Clear the UART1BEINTR interrupt 8 PEIC Parity error interrupt clear Clear the UART1PEINTR interrupt 7 FEIC Framing error interrupt clear Clear the UART1FEINTR interrupt 6 RTIC Receive timeout interrupt clear Clear the UART1RTINTR interrupt 5 TXIC Transmit interrupt clear Clear the UART1TXINTR interrupt 4 RXIC Receive interrupt...

Page 354: ... res res res res res res res res res res res res res res res res res res SPS FEN STP2 EPS PEN BRK Line Control Register reset value 1 1 1 1 1 1 1 1 0x030 UART1CR res res res res res res res res res res res res res res res res CTSEn RTSEn Out2 out1 RTS DTR RXE TXE res res res res res SIRLP SIREN UART1EN Control Register reset value 0 0 1 1 0 0 0 0 0 0 0 0x034 UART1IFLS res res res res res res res r...

Page 355: ...tion UART bidirectional communication requires a minimum of two pins RX TX The frame are comprised of An Idle Line prior to transmission or reception The UART interface uses a baud rate generator A status register UART2_SR data registers UART2DR A baud rate register UART2_B UART1_FBRD Baud rate calculation UART2 can operate with or without using the Fractional Divider The baud rate divisor is a 20...

Page 356: ...0x Reference Manual Version1 1 0 356 399 Figure 54 show how to set the UART Initial value Initial setting Start Set UART2CR TX RX enable END Setting UART baudrate Figure 54 UART2 Initial setting flow chart ...

Page 357: ... res res res res res res res res DATA R W 7 0 DATA Receive READ Transmit WRITE data UART2SR UART2 Status Register Address offset 0x004 Reset value 0x0000_0000 The UART2SR is the status register RXBF and TXBF is read only A write to the UART2SR register clears the TX RX overrun errors 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 ...

Page 358: ...errun Interrupt Enable 4 TOIE Transmit Overrun Interrupt Enable 3 RXIE Receive Interrupt Enable 2 TXIE Transmit Interrupt Enable 1 RXE Receive enable If this bit is set to 1 the receive section of the UART2 is enabled When the UART2 is disabled in the middle of reception it completes the current character before stopping 0 TXE Transmit enable If this bit is set to 1 the transmit section of the UAR...

Page 359: ...register UART2CR 0 TXI Transmit Interrupt This bit depends on the state of the TXIE bit in the control register UART2CR UART2BDR UART2 Baud Rate Divider Register Address offset 0x010 Reset value 0x0000_0000 The UART2BDR r is the integer part of the baud rate divisor value 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res Res res res res res res res res res res res R W 15 14 13 12 11 10 9 8 7 6 5...

Page 360: ...W7500x Reference Manual Version1 1 0 360 399 26 5 Register map The following Table 36 summarizes the UART2 registers Table 36 UART2 register map and reset values ...

Page 361: ...XAS INSTRUMENTS synchronous serial interface A National Semiconductor MICROWIRE interface The SPI interface operates as a master or slave interface It supports bit rates up to 2 MHz and higher in both master and slave configurations The SPI has the following features Parallel to serial conversion on data written to an internal 16 bit wide 8 location deep transmit FIFO Serial to parallel conversion...

Page 362: ...her divided by a factor 1 to 256 through the programming of the SSPCR0 control register to give a final master output clock Transmit FIFO The common transmit FIFO is a 16 bit wide 8 locations deep First In First Out FIFO memory buffer CPU data written across the AMBA APB interface are stored in the buffer until it is read out by the transmit logic When configured as a master or a slave parallel da...

Page 363: ...gister bits Users can also use the individual interrupt requests with a system interrupt controller that provides masking for the outputs of each peripheral In this way a global interrupt controller service routine can read the entire set of sources from one wide register in the system interrupt controller This is attractive when the time to read from the peripheral registers is significant compar...

Page 364: ...signals are not mutually exclusive They can both be asserted at the same time For example when there is more data than the watermark level of four in the receive FIFO the burst transfer request and the single transfer request are asserted When the amount of data left in the receive FIFO is less than the watermark level the single request only is asserted This is useful for situations when the numb...

Page 365: ...RESETn to assert nSSPRST asynchronously and negate it synchronously to SSPCLK PRESETn must be asserted LOW for a period long enough to reset the slowest block in the on chip system and then taken HIGH again The PrimeCell SSP requires PRESETn to be asserted LOW for at least one period of PCLK Configuring the SSP The Following reset the PrimeCell SSP logic is disabled and must be configured when in ...

Page 366: ...s at the right value when the actual sampling occurs within the SSPMS To ensure correct device operation SSPCLK must be at least 12 times faster than the maximum expected frequency of SSPCLKIN The frequency selected for SSPCLK must accommodate the desired range of bit clock rates The ratio of minimum SSPCLK frequency to SSPCLKOUT maximum frequency in the case of the slave mode is 12 and for the ma...

Page 367: ...the external SSPCLK The frame format is programmed through the FRF bits and the data word size through the DSS bits Bit phase and polarity applicable to Motorola SPI format only are programmed through the SPH and SPO bits Programming the SSPCR1 Control Register The SSPCR1 register is used to select master or slave mode enable a loop back test feature enable the PrimeCell SSP peripheral To configur...

Page 368: ...e 24MHz as Max frequency when SSPCLK is 48MHz But 20MHz is recommended as SSPCLKOUT Max frequency for stable CLK output Frame format Each data frame is between 4 16 bits long depending on the size of data programmed and is transmitted starting with the MSB Users can select the following basic frame types Texas Instruments synchronous serial Motorola SPI National Semiconductor Microwire For all for...

Page 369: ...gth in the range of 13 25 bits Texas Instruments synchronous serial frame format Figure 57 shows the Texas Instruments synchronous serial frame format for a single transmitted frame SSPFSSOUT SSPFSSIN SSPTXD SSPRXD 4 to 16 bits SSPCLKOUT SSPCLKIN MSB LSB nSSPOE Figure 57 Texas Instruments synchronous serial frame format single transfer In this mode SSPCLKOUT and SSPFSSOUT are forced LOW and the tr...

Page 370: ...er SPO clock polarity When the SPO clock polarity control bit is LOW it produces a steady state LOW value on the SSPCLKOUT pin If the SPO clock polarity control bit is HIGH a steady state HIGH value is placed on the SSPCLKOUT pin when data is not being transferred SPH clock phase The SPH control bit selects the clock edge that captures data and enables it to change state It has the most impact on ...

Page 371: ...is forced LOW the SSPFSSOUT signal is forced HIGH the transmit data line SSPTXD is arbitrarily forced LOW the nSSPOE pad enable signal is forced HIGH making the transmit pad high impedance when the PrimeCell SSP is configured as a master the nSSPCTLOE line is driven LOW enabling the SSPCLKOUT pad active LOW enable when the PrimeCell SSP is configured as a slave the nSSPCTLOE line is driven HIGH di...

Page 372: ...e slave select pin freezes the data in its serial peripheral register and does not permit it to be altered if the SPH bit is logic zero Therefore the master device must raise the SSPFSSIN pin of the slave device between each data transfer to enable the serial peripheral data write On completion of the continuous transfer the SSPFSSOUT pin is returned to its idle state one SSPCLKOUT period after th...

Page 373: ...ssion lines At the same time the SSPCLKOUT is enabled with a rising edge transition Data is then captured on the falling edges and propagated on the rising edges of the SSPCLKOUT signal In the case of a single word transfer after all bits have been transferred the SSPFSSOUT line is returned to its idle HIGH state one SSPCLKOUT period after the last bit has been captured For continuous back to back...

Page 374: ...e immediately transferred onto the SSPRXD line of the master The nSSPOE line is driven LOW enabling the master SSPTXD output pad One half period later valid master data is transferred to the SSPTXD line Now that both the master and slave data have been set the SSPCLKOUT master clock pin becomes LOW after one additional half SSPCLKOUT period This means that data is captured on the falling edges and...

Page 375: ...ed signal SSPFSSOUT SSPFSSIN SSPRXD 4 to 16 bits SSPCLKOUT SSPCLKIN LSB nSSPOE LSB MSB MSB LSB LSB Q SSPTXD Q MSB Figure 64 Motorola SPI frame format single and continuous transfers with SPO 1 and SPH 1 In this configuration during idle periods the SSPCLKOUT signal is forced HIGH the SSPFSSOUT signal is forced HIGH the transmit data line SSPTXD is arbitrarily forced LOW the nSSPOE pad enable signa...

Page 376: ...and then returns to its idle state as the previous section describes For continuous back to back transfers the SSPFSSOUT pin is held LOW between successive data words and termination is the same as that of the single word transfer National Semiconductor Microwire frame format Figure 65 shows the National Semiconductor Microwire frame format for a single frame SSPFSSOUT SSPFSSIN SSPTXD 4 to 16 bits...

Page 377: ...ck wait state and the slave responds by transmitting data back to the PrimeCell SSP Each bit is driven onto the SSPRXD line on the falling edge of SSPCLKOUT The PrimeCell SSP in turn latches each bit on the rising edge of SSPCLKOUT At the end of the frame for single transfers the SSPFSSOUT signal is pulled HIGH one clock period after the last bit has been latched in the receive serial shifter whic...

Page 378: ...ster can broadcast to the slave through the master PrimeCell SSP SSPTXD line In response the slave drives its SPI MISO port onto the SSPRXD line of the master 0V 0V 0V SSPTXD nSSPOE SSPRXD SSPFSSIN SSPCLKOUT nSSPCTLOE SSPCLKIN MOSI SCK MISO SS SSPFSSOUT Figure 67 PrimeCell SSP master coupled to an SPI slave Figure 68 shows a Motorola SPI configured as a master and interfaced to an instance of a Pr...

Page 379: ...crowire mode TI or Microwire Data Send to Slave Master mode SerialClockRate Setting choose 0 255 DataSize Setting choose 4 16bits SSE Syncronous Serialport Enable Setting End BaudRatePrescaler Setting 4 254 TI or Microwire Data Send to Master Slave mode Mode Setting choose Slave SSE Syncronous Serialport Enable Setting End SOD Slave Output Disable Setting SOD Slave Output Disable Setting Figure 69...

Page 380: ...caler Setting 4 254 SPI Data Send to Master Slave mode Y CPHA 0 N Captured 1 Edge Captured 2 Edge Y CPHA 0 N Captured 1 Edge Captured 2 Edge Mode Setting choose Slave SSE Syncronous Serialport Enable Setting End SOD Slave Output Disable Setting SOD Slave Output Disable Setting Figure 70 how to setting SPI mode flow chart 27 4 SSP0 Registers Base Address 0x4000_A000 This section describes the SSP0 ...

Page 381: ...t data 1011 12 bit data 1100 13 bit data 1101 14 bit data 1111 15 bit data 5 4 FRF Frame Format 00 Motorola SPI frame format 01 TI synchronous serial frame format 10 National Microwire frame format 11 Reserved undefined operation 6 SPO SSPCLKOUT polarity This is applicable to Motorola SPI frame format only 7 SPH SSPCLKOUT phase This is applicable to Motorola SPI frame format only 15 8 SCR Serial c...

Page 382: ...e mode select 0 device configured as master default 1 device configured as slave 3 SOD Slave mode output disable This bit is relevant only in the slave mode MS 1 In multiple slave systems it is possible for a SSP0 master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto its serial output line In such systems the RXD lines from multiple slaves co...

Page 383: ...alue 0x0000_0003 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res BSY RFF RNE TNF TFE R W R W R W R W R W 0 TFE Transmit FIFO empty RO 0 Transmit FIFO is not empty 1 Transmit FIFO is empty 1 TNF Transmit FIFO not full RO 0 Transmit FIFO is full 1 Transmit...

Page 384: ...ending on the frequency of SSPCLK The least significant bit always returns zero on reads SSP0 Interrupt mask set or clear register SSP0IMSC Address offset 0x0014 Reset value 0x0000_00000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res TXI M RXI M RTI...

Page 385: ... 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res TXRI S RXRI S RTRI S ROR RIS R W R W R W R W 0 RORRIS Gives the raw interrupt state prior to masking of the SSPRORINTR interrupt 1 RTRIS Gives the raw interrupt state prior to masking of the SSPRTINTR interrupt 2 RXRIS Gives the ra...

Page 386: ...mit FIFO masked interrupt state after masking of the SSPTXINTR interrupt SSP0 Interrupt clear register SSP0ICR Address offset 0x0020 Reset value 0x0000_00000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res RTIC ROR IC R W R W 0 RORICS Clears ...

Page 387: ...res res res res res res res res res res res res res TXD MAE RXD MAE R W R W 0 RXDMAE Receive DMA Enable 0 DMA for the receive FIFO is disabled 1 DMA for the receive FIFO is enabled 1 TXDMAE Transmit DMA Enable 0 DMA for the transmit FIFO is disabled 1 DMA for the transmit FIFO is enabled ...

Page 388: ...W7500x Reference Manual Version1 1 0 388 399 27 5 Register map The following Table 38 summarizes the SSP0 registers Table 38 SSP0 register map and reset values ...

Page 389: ... W R W R W 3 0 DSS Data size select 0000 reserved undefined operation 0001 reserved undefined operation 0010 reserved undefined operation 0011 4 bit data 0100 5 bit data 0101 6 bit data 0110 7 bit data 0111 8 bit data 1000 9 bit data 1001 10 bit data 1010 11 bit data 1011 12 bit data 1100 13 bit data 1101 14 bit data 1111 15 bit data 5 4 FRF Frame Format 00 Motorola SPI frame format 01 TI synchron...

Page 390: ... W R W R W 0 LBM Loop back mode 0 normal serial port operation enabled 1 output of transmit serial shifter is connected to input of receive serial shifter internally 1 SSE Synchronous serial port enable 0 SSP1 operation disabled 1 SSP1 operation enabled 2 MS Master or Slave mode select 0 device configured as master default 1 device configured as slave 3 SOD Slave mode output disable This bit is re...

Page 391: ...W7500x Reference Manual Version1 1 0 391 399 1 SSP1 must not drive the SSPTXD output in slave mode ...

Page 392: ...ed bits at the top are ignored by transmit logic The receive logic automatically right justifies SSP1 Status register SSP1SR Address offset 0x000C Reset value 0x0000_0003 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res BSY RFF RNE TNF TFE R W R W R W R W...

Page 393: ...3 2 1 0 res res res res res res res res CPSDVSR R W R W R W R W R W R W R W R W 7 0 CPSDVSR Clock prescale divisor This must be an even number from 2 254 depending on the frequency of SSPCLK The least significant bit always returns zero on reads SSP1 Interrupt mask set or clear register SSP1IMSC Address offset 0x0014 Reset value 0x0000_00000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res ...

Page 394: ...Raw interrupt status register SSP1RIS Address offset 0x0018 Reset value 0x0000_00004 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res TXRI S RXRI S RTRI S ROR RIS R W R W R W R W 0 RORRIS Gives the raw interrupt state prior to masking of the SSPRORINT...

Page 395: ...mit FIFO masked interrupt state after masking of the SSPTXINTR interrupt SSP1 Interrupt clear register SSP1ICR Address offset 0x0020 Reset value 0x0000_00000 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 res res res res res res res res res res res res res res res res 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 res res res res res res res res res res res res res res RTIC ROR IC R W R W 0 RORICS Clears ...

Page 396: ... res res res res res res res res TXD MAE RXD MAE R W R W 0 RXDMAE Receive DMA Enable 0 DMA for the receive FIFO is disabled 1 DMA for the receive FIFO is enabled 1 TXDMAE Transmit DMA Enable 0 DMA for the transmit FIFO is disabled 1 DMA for the transmit FIFO is enabled ...

Page 397: ...W7500x Reference Manual Version1 1 0 397 399 27 7 Register map The following Table 39 summarizes the SSP1 registers Table 39 SSP1 register map and reset values ...

Page 398: ...Edit PADCON register description CS DS inverted value Ver 1 0 5 17NOV2017 Edit UARTCR register description about UARTEN Ver 1 0 6 29NOV2017 Edit WZTOE Sn_KATMR description about timer trigger Ver 1 0 7 26JAN2018 Edit typo about PWM preodic mode Ver 1 0 8 12FAB2018 Edit Base Address about RTC 4000_4000 4000_E000 Ver 1 0 9 05MAR2018 Edit UART2 description register map Ver 1 1 0 11APR2018 Edit Systic...

Page 399: ... Version1 1 0 399 399 Copyright Notice Copyright 2018 WIZnet Co Ltd All Rights Reserved Technical Support https forum wizwiki io Sales Distribution sales wiznet io For more information visit our website at http www wiznet io ...

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