UNIFREM v.3.41x
10 May 2017
Page 164 from 180
9.2 Example of logical blocks setting
UNIFREM frequency converters have rich possibilities of logical blocks, with logical operations
setting in their software equipment: OR, AND, XOR, RS , = , >=, >.
Logical blocks inputs and outputs types setting possibility:
(
output negated
,
logical block
input 1 negated, logical block
input 2 negated
, first LB input
responds to the rising edge of the signal, second LB input responds to the rising edge of the
signal).
Example of logical block inputs and outputs configuration options:
Example:
This following example demonstrates a simple example for the converter setting by using logical
blocks. Asynchronous motor with power 0.37 [kW] and rated current [A] 1.05[A] is controlled. We
consider the positive linear frequency ramp-up (10[s] duration) of unloaded motor from the zero
frequency to the setpoint frequency of 50 [Hz]. Ramp-down of the motor is realised with linear
ramp (10[s] duration) to the zero frequency.
Ramp-up and ramp-down setting for this example
Converter setting by using logical blocks: The goal is to evaluate and signalize frequency 20 [Hz]
crossing and not exceeding the motor current 1 [A] (motor is unloaded). Converter indicates this
conditions in a special way - with analog output switching. Analog output gets character of relay
output. The output of the logical block LB1 with the logical operation AND has logical value 1 over
the frequency of the motor 20 [Hz] and at the motor current <1 [A]. LB1 output signal enters the
second logical block LB2. Progress of the output LB2 signal (discrete states alternating of the
