UNI-T UPO2000CS Series, User Manual

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UPO2000CS series User Manual
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CS is usually effective low. It should kept low level during the entire transmission.
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Clock signal SCK has two kinds of polarity:

CPOL=0. If the clock is idle, the clock level is low.

CPOL=1. If the clock is idle, the clock level is high.

The clock phase also has two kinds to select.

If CPHA is 0, the front edge of the clock cycle will collect data.

If CPHA is 1, the back edge of the clock cycle will collect data.
Note: As to the start and end position, the first data of MOSI and MISO in the practical application, different application
situations have different requirements. The UPO 2000CS oscilloscope can help you conveniently analyze the waveform
trigger of critical positions.
SPI: Start SPI trigger
Press DECODE at the right corner. And then press the TYPE option key to open protocol type list. Rotate
Multipurpose
knob to select to SPI protocol mode. Press
Multipurpose
knob to start the SPI protocol mode.
CS Setting: Set Chip Selection Enable Signal
Use this feature to enter the enable signal setting up interface. Press the CS SOURCE option button to switch any
channel among CH1-CH4 as chip selection signal. The corresponding logic level can be adjusted when the corresponding
signal source is selected. The way of adjusting is the same with that of trigger level. To avoid the effect of signal noise, it
is suggested that the comparative level should be set in the waveform center area to obtain the accurate captured
result. Press the CS POLARITY option button to set the positive or negative polarity of the chip selection signal. The
normal SPI communication uses the transmission signal with negative polarity.
SCLK setting: Set the Clock Signal
Use this function to enter the clock signal setting interface. Press the SCLK button to switch any channel among