Transtech Transputer, User Manual

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The TMB14 Motherboard
TMB M 711 Transputer Motherboard User Manual
95
8.2.2 Subsystem Control Registers
The subsystem control registers allow the error states of the eight
TRAMs to be determined. They also allow the subsystem port
VMEReset and VMEAnalyse signals to be set and cleared.
• Subsystem Reset/Error Register: bit 0 of this register returns the
state of the
notVMEError signal (active low) when read. Writing
to this bit controls the state of VMEReset . This is asserted when
set. Bits 1-7 are not used.
• Subsystem Analyse Register: writing to bit 0 of this register
controls the state of
VMEAnalyse . It is asserted when set. Bits 1-
7 are not used.
• TRAM Error Register: reading this register returns the state of the
error lines from the eight TRAMs. The bit position corresponds to
the TRAM slot number, hence bit 0 reflects slot 0’s error line and
so on. (These bits are active low).
8.2.3 Interrupt Control Registers
Programming the interrupt control registers allows the user to
determine which (if any) of three events will cause a VMEbus
Byte Offset Bits R/W Description
#09 0 Read notVMEError
Write VMEReset
#0B 0 Write VMEAnalyse
#13 0 to 7 Read TRAM errors
Table 34: Subsystem Control Registers