Transtech Transputer, User Manual

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Link and Control Configuration
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Transputer Motherboard User Manual TMB M 711
interrupt, the level of such an interrupt and the vector number
returned during an interrupt acknowledge cycle:
• Interrupt Enable Register: bits 1-3 of this register are used to
enable interrupts due to active notVMEError, C012 output ready,
and C012 input ready respectively. To enable an interrupt the
appropriate bit must be set. This register is zeroed at power on or
during a VMEbus SYSRESET* condition.
• Interrupt Level Register: the value in bits 0-2 of this register
determines the level of any VMEbus interrupt generated by the
TMB14. The value corresponds directly to one of the seven
interrupt lines IRQ1*-IRQ7*. A value of zero will effectively
disable interrupts. This register is zeroed at power on or during a
VMEbus SYSRESET* condition. It may be written and read.
• Interrupt Status/ID Register: the value in this 8 bit register is
returned during an interrupt acknowledge cycle. It may be written
and read. This register is more generally known as the Vme
Interrupt Vector
8.3 Link and Control Configuration
Almost all of the link connections between the TRAM slots and the
edge connectors are determined by the two C004 link switches. The
exceptions are made by hardware jumper settings.
The subsystem connections between the TRAMs, the host computer
and the edge connector are configurable by hardware jumper
settings.
Byte Offset Bits R/W Description
#0D 1 Write Error Interrupt Enable
2 Write Output Interrupt Enable
3 Write Input Interrupt Enable
#0F 0 to 2 R/W Interrupt Level
#11 0 to 7 Read Interrupt Status/ID
Table 35: Interrupt Control Registers