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Description

78

Transputer Motherboard User Manual

TMB M 711

Pin

c

b

a

edge L0

IC3linkout0

IC2linkin0

GND

edge L1

IC3linkout2

IC2linkin2

GND

edge L2

IC2linkout4

IC3linkin4

GND

edge L3

IC2linkout5

IC3linkin5

GND

edge L4

IC2linkout6

IC3linkin6

GND

edge L5

IC2linkout3

IC3linkin3

GND

edge L6

IC3linkout1

IC2linkin1

GND

edge L7

IC3linkout7

IC2linkin7

GND

edge L8

IC3linkout29

IC2linkin29

GND

edge L9

IC3linkout30

IC2linkin30

GND

edge L10

IC2linkout31

IC3linkin31

GND

edge L11

IC2linkout28

IC3linkin28

GND

edge L12

IC3linkout24

IC2linkin24

GND

edge L13

IC2linkout25

IC3linkin25

GND

edge L14

IC2linkout26

IC3linkin26

GND

edge L15

IC3linkout27

IC2linkin27

GND

edge L16

IC3linkout17

IC2linkin17

GND

edge L17

IC2linkout19

IC3linkin19

GND

edge L18

IC2linkout22

IC3linkin22

GND

edge L19

IC3linkout23

IC2linkin23

GND

edge L20

IC2linkout16

IC3linkin16

GND

edge L21

IC2linkout18

IC3linkin18

GND

edge L22

IC3linkout21

IC2linkin21

GND

edge L23

IC3linkout20

IC2linkin20

GND

edge L24

IC3linkout10

IC2linkin10

GND

edge L25

IC3linkout13

IC2linkin13

GND

edge L26

IC3linkout14

IC2linkin14

GND

edge L27

IC3linkout11

IC2linkin11

GND

edge L28

IC2linkout8

IC3linkin8

GND

edge L29

IC2linkout9

IC3linkin9

GND

edge L30

IC2linkout12

IC3linkin12

GND

edge L31

IC2linkout15

IC3linkin15

GND

Table 27: P1 connector pinout

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Summary of Contents for Transputer

Page 1: ...Transputer Motherboard User Manual Ref TMB M 711...

Page 2: ...serves the right to alter specifications without notice in line with its policy of continuous development Transtech cannot accept responsibility to any third party for loss or damage arising out of th...

Page 3: ...pects 10 2 3 2 Topology Aspects 11 2 3 3 Network Configuration Aspects 13 2 4 Summary 14 Chapter 3 The TRAM Standard 17 3 1 Introduction 17 3 2 The Transputer Module 18 3 2 1 Overview 18 3 2 2 Functio...

Page 4: ...iguration Jumpers 47 5 3 1 On board transputer clock and memory 48 5 3 2 Control Configuration 49 5 3 3 Board IO Address 50 5 3 4 Link Speed Configuration 51 5 3 5 Master and Slave Configuration 52 5...

Page 5: ...91 8 2 VMEbus Interface 93 8 2 1 Link Adaptor Registers 94 8 2 2 Subsystem Control Registers 95 8 2 3 Interrupt Control Registers 95 8 3 Link and Control Configuration 96 8 3 1 Links 97 8 3 2 Subsyst...

Page 6: ...Operation of the Software 133 Chapter 10 The TMB17 Motherboard 135 10 1 Overview 135 10 2 Windows 95 136 10 3 PCI Interface 137 10 3 1 Hardware Description 137 10 3 2 Register Map 137 10 3 3 PCI Conf...

Page 7: ...11 7 Transputer host I O utilities 162 11 8 Inmos Aserver Support 163 11 9 Solaris 2 Device Driver 164 11 10 Reference Manual Pages 166 11 10 1 Commands 166 check 1 166 ckmon 1 168 ftest 1 169 iserve...

Page 8: ...vi Transputer Motherboard User Manual TMB M 711...

Page 9: ...tains more advanced information required for fault finding designing compatible hardware or for systems programming Chapter 4 describes the TMB03 low cost motherboard for PC Chapter 5 describes the TM...

Page 10: ...Introduction 2 Transputer Motherboard User Manual TMB M 711 Chapter 12 provides a detailed trouble shooting guide...

Page 11: ...TRAMs TRAMs are small assemblies based on transputers with a standard electrical and mechanical interface They plug onto standard motherboards which in turn plug into or can be connected to a range o...

Page 12: ...ientation purposes See figure 1 Some TRAMs have a subsystem this consists of three zero profile sockets mounted on the underside of the TRAM in one corner always next to pin 1 Only slot 0 on the mothe...

Page 13: ...onto a motherboard is called a slot or site Slots are numbered from zero Figure 3 shows a slice of a typical motherboard Note that the slots are not all oriented the same way and that the ordering of...

Page 14: ...do not use all of the sites underneath them The only active site is the one below pin 1 of the TRAM This means that the pipeline is broken at the unused slots underneath the TRAM To bridge these break...

Page 15: ...ding the system consists of three main stages 1 Plug the TRAMs onto the motherboard 2 Configure the motherboard reset structure for the software devel opment system or application being used 2 2 1 Phy...

Page 16: ...of the motherboard TRAM combination However please bear in mind that adequate airflow under the TRAM is required for cooling See figure 7 2 2 2 Configuring the System The next stage is to set all the...

Page 17: ...r This configuration is suitable for occam TDS users and also for Inmos toolset users who wish to use the interactive debugger where a program i e the TDS runs on the master processor while other proc...

Page 18: ...st computer interface and therefore has to be slaved to a master There are three aspects to connecting up several motherboards 1 Sorting out the control system 2 connecting up the transputers 3 connec...

Page 19: ...s toolsets 2 3 2 Topology Aspects In order for the transputers to communicate their links must be connected together In keeping with the pipeline connections made within a single motherboard when seve...

Page 20: ...d PipeTail Hence you must connect the PipeTail of one board to the PipeHead of the next board Because the PipeTail to PipeHead connection is actually a transputer link the cable used to make this conn...

Page 21: ...ontrolled by transputer s on the motherboards called configuration transputers The configuration transputers from different motherboards are connected together into a pipeline called the configuration...

Page 22: ...single motherboard and multi motherboard computing systems from TRAMs This chapter has given a statement of the actions to be performed in constructing TRAM based systems often without explaining exac...

Page 23: ...Manual 15 why those actions are necessary This is in keeping with a beginners introduction For an explanation of the underlying system read Chapter 3 which gives details of the TRAM standard and can...

Page 24: ...Summary 16 Transputer Motherboard User Manual TMB M 711...

Page 25: ...ted communications circuitry which enables a complete computing engine to be constructed from more than one device In this sense the transputer is very much a building block of large parallel computer...

Page 26: ...erview A TRAM is a self contained computing subsystem Physically it is small and will contain either a transputer or some other device which connects via INMOS links TRAMs interface to each other via...

Page 27: ...ng the signal it becomes notError and also makes the signal an open collector output This allows wire ORing of the error signals allowing any TRAM to signal error back to the host computer The other p...

Page 28: ...stem to the motherboard a special double ended subsystem port connector is used This is shown in figure 2 This arrangement reflects the optionality of subsystem pins on the TRAM and ensures that TRAMs...

Page 29: ...edance to that of the transmission line to which it is connected The NotError output is an inverted buffered open collector version of the transputer s error flag Other connections require no special...

Page 30: ...ected together in a separate pipeline the first module in the pipeline on a given motherboard can control a subsystem of other modules that may reside on the same motherboard another motherboard or be...

Page 31: ...ither on the motherboard or on a TRAM and connects link1 of that slot to link2 of that slot 3 3 2 2 Programmable Link Configuration Some motherboards have a number of C004 link crossbar switches mount...

Page 32: ...boards is achieved by edge connections ConfigUp and ConfigDown figure 23 Usually the link switch configuration data will originate from the a module on the first motherboard in the system Hence one of...

Page 33: ...tware for electronic link configuration 3 3 3 System Control The design requirements of the motherboard part of the TRAM standard stated that a hierarchical control structure be provided to control ne...

Page 34: ...is left unconnected Within a motherboard there are options as to what source controls the TRAMs on that motherboard Module0 can be controlled from either the host computer or from an external source...

Page 35: ...Up Down Subsystem Large networks are built up by connecting motherboards together For this purpose each motherboard has three control ports up control in source of external control down control out e...

Page 36: ...e of processors on boarda as well as the first processor on each of boardb and boarde Two of the processors in this master network control their own subnetworks The first subnetwork consists of the pr...

Page 37: ...the master E g processors on boardc d can send error back to their master boardb in figure 27 above The notError signal arriving at a subsystem port is not propagated to the up port but is handled by...

Page 38: ...sing subsystems the corresponding signal is held asserted for at least 5 ms In the case of reset the subsystem should be left for a further 5 ms before attempting to boot it 3 4 Host Computer Interfac...

Page 39: ...in the following sections IO Address Register boardbase 00 InputDataRegister boardbase 01 OutputDataRegister boardbase 02 InputStatusRegister boardbase 03 OutputStatusRegister boardbase 10 Reset regi...

Page 40: ...software to see if any data has arrived When the data register is read the flag in the status register is cleared Output to the link from the PC follows a similar pattern An in use flag in the Output...

Page 41: ...ers provide support for allowing DMA access to the link hardware This overcomes the inherent inefficiency of software polling for every single byte read or written to the link adapter however these fe...

Page 42: ...controller It is possible to share DMA channel 2 with the floppy disk controller by careful programming of the floppy disk controller enable flag located at IO address space 3F2 Whenever a floppy disk...

Page 43: ...l PC hosted TRAM motherboard with space to plug in up to five Transputer Modules It has a dummy site allowing a size six TRAM to be fitted It is possible to use the TMB03 without TRAMs as a driver boa...

Page 44: ...are briefly described below and in detail in the following sections IBM UP The source of control for the TRAM in slot0 can be from either the host PC or from the edge connector UP Mod0SS The TRAMs in...

Page 45: ...IO base address is achieved via jumpers AS0 AS1 as follows Jumper in out Description IBM UP out Slot 0 is controlled by the PC default in Slot 0 is controlled by the edge connector up port Table 3 Slo...

Page 46: ...il PipeHead connection can be made regardless of the master slave configuration By altering the M S jumpers it is possible to connect module0 link0 to the edge connector as an external link as long as...

Page 47: ...ved See figure 30 on page 35 for the location of the C012 Permanent damage may result if you do not remove the C012 when configuring the TMB03 as a slave or if you use the master SLAVE configuration M...

Page 48: ...alter the defaults cut the existing tracks and hook up the solder pads as required It is possible to configure the board to use DMA channels 1 2 or 3 and to use interrupts 3 4 5 6 7 or 9 To disable th...

Page 49: ...3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 downAnalyse master linkin module4 link2in subsystemError subsystemReset module4 link3out module4 link0out modul...

Page 50: ...tially the connector brings out the three control ports the link0s and link3s of all the transputers for network configuration and the ends of the default pipeline This is summarized for reference pur...

Page 51: ...ard normal operation board set to master mode master link connected to an external rack of transputer equipment no TRAM in slot0 of the board use as a link adapter card board set to slave mode master...

Page 52: ...o subsystem pins are needed Fit the boards in your PC and using the hedgehog breakout boards make the following connections Power on the PC and run check When connecting the TMB03 to motherboards whic...

Page 53: ...ce and four TRAM sites The board has been designed to support transputer clock speeds from 17 5 to 35 MHz and the memory access time can be set to 3 4 5 or 6 cycles This allows the matching of many di...

Page 54: ...0 and 1 and the TRAM has components on its underside use of an additional set of spacers is recommended to avoid overheating the transputer there are no holes in the board so the TRAMs cannot be secur...

Page 55: ...ed either from the subsystem of the on board transputer or from the source which controls the transputer In the following sections it is assumed that you are holding the board component side up with t...

Page 56: ...The correct setting depends on the SIMM s row access time TRAC the clock speed of the transputer as set by SW2 and on the number of SIMMs fitted SW2 4 SW2 5 SW2 6 Processor clock on off off 17 5 MHz o...

Page 57: ...on board transputer and the modules in slots 0 to 3 to be determined The control consist of the TRAM signals reset error and analyse Note that subsystem pins are not needed with the TMB04 the on boar...

Page 58: ...ollows Jumper Position Description LK12 Left Slots 0 to 3 are controlled from the transputer s subsystem port default Right Slots 0 to 34 are controlled from the same source as the transputer Table 14...

Page 59: ...ection switch Switch Position Description SW1 7 on Links at 10 MBits s off Links at 20 MBits s default Table 18 TRAM slots 0 to 3 link speed selection switch SW 2 1 SW 2 2 SW 2 3 on board transputer l...

Page 60: ...SW1 as follows Jumper Position Description LK5 Left transputer link 0 connected to PC interface default Right transputer link 0 connected to D type connector L0 on the hedgehog Table 20 On board tran...

Page 61: ...23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 downAnalyse slot 0 link 3 in slot 3 link 2 in subsystemError subsystemReset slot 0 link 1 out slot 3 link 3 out slot 3 link 0 in slot 1 link...

Page 62: ...and the ends of the default pipeline This is summarized for reference purposes in figure 42 Note that to connect a link of the on board transputer to one of the TRAM slots the link must be looped bac...

Page 63: ...rboard TMB M 711 Transputer Motherboard User Manual 55 0 1 2 3 S0 Host Figure 42 Summary of Network interconnect 0 1 2 3 S1 0 1 2 3 S2 0 1 2 3 S3 L9 L11 L5 L6 L7 L8 PC L0 L4 0 1 2 3 on board L1 L3 tra...

Page 64: ...The Edge Connector 56 Transputer Motherboard User Manual TMB M 711...

Page 65: ...p to ten Transputer Modules The TMB08 is shipped with an IMSC004 link switch which provides for setting up user defined topologies The switch is flexible enough to allow any TRAM s link 0 or 3 to be c...

Page 66: ...This section describes the organization of the electronic link switch the IMSC004 In this application the C004 is used simply as a crossbar switch The device is connected to 30 links and can switch a...

Page 67: ...nk7 link8 link9 link10 link11 link12 link13 link14 link15 link16 link17 link18 link19 link20 link21 link22 link23 link24 link25 link26 link27 link28 link29 module1 L0 module2 L0 module3 L0 module4 L0...

Page 68: ...gether for the first motherboard in a system or to take them off the board for a slave motherboard The links taken to the patch area are ConfigUp i e link1 of the configuration processor PipeHead i e...

Page 69: ...Motherboard TMB M 711 Transputer Motherboard User Manual 61 C004 L29 patch1 slot0 link1 T2 Config patch0 C004 L28 Figure 47 TMB08 Patch Area connections for slave board root T2 C004 module0 L1 L3 L1...

Page 70: ...1 Board Configuration The basic board configuration is achieved by the use of the configuration switches In the top right hand corner of the board there is a 6 way switch bank Switch 1 is on the righ...

Page 71: ...ible options are shown in Figure 49 Figure 49 Board address options 6 3 1 3 Control Configuration There are two configuration options relating to board control S4 MD0 source of control for modules1 to...

Page 72: ...egister At base address 14 This is a read write register so that the programmed selection can be read back The register coding is as shown in figure 51 and figure 52 module 0 edge connector source of...

Page 73: ...to a 8 bit only slot then only IQR 3 or 5 and DMA 1 or 3 can be used 6 3 3 The Edge Connector On the right hand edge of the TMB08 is a 37 way D type edge connector On the TMB08 the edge connector is u...

Page 74: ...35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 downAnalyse ConfigDown in PipeTail in subsystemError subsystemReset patch link1out patch link0out edge...

Page 75: ...L28 patch1 to C004 L29 The patch0 1 connections allow 10 links to be brought out from the C004 to the edge connector down subsystem ConfigDown PipeTail patch link1 patch link0 edge link7 edge link6 ed...

Page 76: ...connected as a single system configured for use with an Inmos Toolset 6 4 1 Stand alone TMB08 The most common stand alone configuration for the TMB08 is for use with the Inmos Toolsets with every TRAM...

Page 77: ...connected the configuration pipeline needs to be connected First set up one board with the same configuration as for stand alone operation see above Ensure that pipe jumpers are used in empty TRAM slo...

Page 78: ...board should be set up as follows Switches Setting Description S1 S2 on off Bus address 200 S3 off Use 20 Mbit s links S4 on Slots 1 to 9 controlled from same source as slot 0 S5 on Slot 0 controlled...

Page 79: ...1 Plug both boards into the PC and fit hedgehogs and make the following connections between the boards Cable First board Second board Reset Cable Down DN Up UP Link Cable Pipetail L10 Patch 1 L9 Link...

Page 80: ...Examples 72 Transputer Motherboard User Manual TMB M 711...

Page 81: ...ny host computer Connection to other transputer systems is achieved via an edge connector which brings 32 links out of the board Board services power configuration and system services are also brought...

Page 82: ...out of TRAM sites on the motherboard for reference Figure 58 shows the general board layout including configuration jumpers and switches for reference Slot1 Slot2 Slot3 Slot4 Slot5 Slot6 Slot7 Slot8 S...

Page 83: ...cribed very briefly here P1 carries 32 transputer links off the board P2 carries power pipeline and configuration links and system control signals off the board K1 allows the default pipeline to be br...

Page 84: ...he P1 Edge Connector The TMB12 has two edge connectors called P1 and P2 Both of these connectors are standard DIN41612 96 way connectors Ensure that when wiring to one of these connectors you do not S...

Page 85: ...es with a break out board in the cable pack This plugs into the P1 edge connector and brings the links out onto standard link plugs 7 2 3 The P2 Edge Connector Edge connector P2 carries the power supp...

Page 86: ...L13 IC2linkout25 IC3linkin25 GND edge L14 IC2linkout26 IC3linkin26 GND edge L15 IC3linkout27 IC2linkin27 GND edge L16 IC3linkout17 IC2linkin17 GND edge L17 IC2linkout19 IC3linkin19 GND edge L18 IC2li...

Page 87: ...GND GND GND 11 nc nc nc 12 GND GND GND 13 nc nc nc 14 IC1linkout1 IC3linkout22 IC1linkout2 15 IC1linkin1 IC2linkin22 IC1linkin2 16 GND GND GND 17 nc nc nc 18 P4 3 nc P4 2 19 P4 4 nc nc 20 P4 5 GND nc...

Page 88: ...IC1linkout2 IC1linkin1 IC2linkin22 IC1linkin2 P4 3 nc P4 2 P4 4 nc nc P4 5 GND nc P4 6 notSubReset P4 7 K1 11 notSubAnalyse P4 8 K1 10 notSubError P4 9 GND P4 10 nc nc GND nc notUpReset notDownReset n...

Page 89: ...ible with the power supply socket on most disk units and can be used to drive such peripherals From top to bottom the pins are The pins are rated for currents up to 3Amps 7 2 4 3 Uncommitted Pins Nine...

Page 90: ...ted to 16 inputs of one of the C004s IC2 The link input signals from all the link3s on all the slots 16 signals are connected to 16 of the outputs of the same C004 The C004 can therefore switch any li...

Page 91: ...general wiring scheme between the TRAM slots and the switches figure 62 the connections to the T2 configuration processor and table 30 shows the link wiring in full detail Unless otherwise stated the...

Page 92: ...il Slot Edge Connector Links L0Out L3Out IMSC004 IC3 L3In L0In L1 L2 L0Out L3Out L3In L0In Slot Edge Connector Links IMSC004 IC2 Figure 61 Connection details of the link switches 0 15 T2 IC2 IC3 confi...

Page 93: ...25 in 14 edge L26 out slot8 L3 in slot8 L3 out edge L26 in 15 slot 11 L0 out edge L3 in edge L3 out slot 11 L0 in 16 slot 7 L0 out edge L20 in edge L20 out slot 7 L0 in 17 edge L16 out slot 3 L3 in sl...

Page 94: ...he K1 header block By default this header is jumpered such that the four sub pipelines are connected together into one long pipeline The default pipeline is split at locations 3 4 7 8 and 11 12 Also t...

Page 95: ...nnecting transputer link0 s together then this can be achieved by wiring the transputer links to the edge connector and using a short link cable to jumper the break out board Clearly transputer link0s...

Page 96: ...9 type 0 edge L25 type 0 edge L10 type 3 edge L26 type 0 edge L11 type 3 edge L27 type 0 edge L12 type 0 edge L28 type 3 edge L13 type 3 edge L29 type 3 edge L14 type 3 edge L30 type 3 edge L15 type 0...

Page 97: ...ese sub pipelines are connected together into one long pipeline slot0 link0 is taken directly to edge connector P2 Also taken to P2 is the C004 link that it would have been expected to be wired to In...

Page 98: ...f the board bypassing the electronic switches Figure 66 shows the main relations between P2 K1 and the link switches 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 T2 30b 29b 23b 24b 3 18 11 10 16c 15c 16a 15a...

Page 99: ...een the TRAMs are controlled by a pair of C004 link switches 24 links are taken from these to edge connectors on the board This arrangement allows almost any network topology to be adopted The board a...

Page 100: ...link interconnections Because there are two C004 s for eight TRAM slots all the TRAM links are reconfigurable It is therefore possible to emulate the hard wired pipeline connecting links 1 and 2 of e...

Page 101: ...n INT 1 7 DO8 O interrupter It maps a number of registers into consecutive odd locations in the short address space starting at a base address set by switches SW1 2 These registers correspond to a C01...

Page 102: ...ses Bits 2 7 are not used and must be written as zero s Output Data Register data written to this register is transmitted out of the VMEbus link Data may only be written when the Output Ready flag in...

Page 103: ...not used Subsystem Analyse Register writing to bit 0 of this register controls the state of VMEAnalyse It is asserted when set Bits 1 7 are not used TRAM Error Register reading this register returns...

Page 104: ...fectively disable interrupts This register is zeroed at power on or during a VMEbus SYSRESET condition It may be written and read Interrupt Status ID Register the value in this 8 bit register is retur...

Page 105: ...sary may be daisy chained and all of their link switches programmed from the head of the pipeline 8 3 1 2 Link Switches There is a program available to automate the process of making soft link connect...

Page 106: ...make one of the 9 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20...

Page 107: ...Figure 72 illustrates the possible connections with the three signals represented as a single bus line The switches are shown as they would be with the relevant jumper installed Removing the jumper mo...

Page 108: ...nd Control Configuration 100 Transputer Motherboard User Manual TMB M 711 TRAMs 1 7 TRAM 0 VMEbus Subsystem J8 J9 J10 J11 P4 P5 P2 P2 ServicesUp ServicesDown TRAM 0 Subsystem Figure 72 Subsystem Conne...

Page 109: ...side by side and KA JD are 3 pin requiring a jumper to be fitted between the central pin and the left or right or right hand pin SW1 and SW2 are sixteen position rotary switches 01 2 3 4 5 6 7 8 9 A...

Page 110: ...is 0xXY00 and on earlier revisions is 0xYX00 8 4 2 Link Speed Configuration The speeds of the transputer links are set as follows Note that J4 and J5 must have the same setting and so must J6 and J7 h...

Page 111: ...rries the same controls signals as slots 1 to 7 so it is not possible to construct a hierarchical control structure with more than one board J8 J9 Description in don t care Slot 0 is controlled from t...

Page 112: ...the configuration pipeline to be taken to either the front or back of the board In the left Jumpers in Jumpers out Description JA JF JI T2 link 1 connected to ConfigUp JB JC JD JE JF VMEbusLink conne...

Page 113: ...f the board 8 5 Connector Pinouts The following tables give the pin assignments for the TMB14 s edge connectors Note that P2 is arranged so that standard link cables may be inserted onto the pins at t...

Page 114: ...D 10 SYSFAIL BG3IN SYSCLK 11 BERR BG3OUT GND 12 SYSRESET BR0 DS1 13 LWORD BR1 DS0 14 AM5 BR2 WRITE 15 A23 BR3 GND 16 A22 AM0 DTACK 17 A21 AM1 GND 18 A20 AM2 AS 19 A19 AM3 GND 20 A18 GND IACK 21 A17 SE...

Page 115: ...GND A31 GND 12 nc GND nc 13 P2Link2Out 5V P2Link3Out 14 P2Link2In D16 P2Link3In 15 GND D17 GND 16 GND D18 GND 17 nc D19 nc 18 P2Link4Out D20 P2Link5Out 19 P2Link4In D21 P2Link5In 20 GND D22 GND 21 GN...

Page 116: ...Connector Pinouts 108 Transputer Motherboard User Manual TMB M 711 Pin Description 1 12V 2 12V 3 GND 4 5V Table 45 P3 User power connector pin assignments...

Page 117: ...7 6 5 4 3 2 1 Figure 74 P4 top D type pinout notUpReset notUpError P4Link0In P4Link1In P4Link2Out P4Link3Out P4Link4Out GND P4Link5In P4Link6In P4Link7In FrontConfigUpOut ConnectorLinkOut nc nc nc nc...

Page 118: ...9 8 7 6 5 4 3 2 1 Figure 75 P5 bottom D type pinout nc nc P5Link0In P5Link1In P4Link2Out P5Link3Out P5Link4Out GND P5Link5In P5Link6In P5Link7In nc nc FrontConfigDownIn notDownAnalyse nc nc nc GND nc...

Page 119: ...ser Manual 111 nc nc nc nc Connector link Config Up P4 link7 P4 link6 P4 link5 P4 link4 P4 link3 P4 link2 P4 link1 P4 link0 up DN SU L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 UP circuit board stencilling...

Page 120: ...appear at the offsets shown from a base address set by SW1 SW2 The base address is XY00 in the short address space where X is set by SW2 and Y by SW1 down nc ConfigDown nc nc nc P5 link7 P5 link6 P5...

Page 121: ...e will cause a bus error as recommended by the VMEbus specification Offset hex Register 01 C012 input data register 03 C012 output data register 05 C012 input status register 07 C012 output status reg...

Page 122: ...Programming 114 Transputer Motherboard User Manual TMB M 711...

Page 123: ...e TMB16 has a further reconfigurability option via the patch area which allows it to be the master board in a multi board system or a slave board in a multi board system It is also possible to arrange...

Page 124: ...shows the TRAM layout of this board Figure 79 shows the location of the switches patch area and connectors of the board 9 2 Network Configuration This section provides an overview of network configura...

Page 125: ...are link0 of all TRAM slots except module0 module0 link0 is connected to the host PC via the T2 link3 of all TRAM slots eight edge connectors two spare links which are taken to the patch area The conn...

Page 126: ...ot processor is connected to another TRAM motherboard via PipeHead in a multi board system To this end six transputer links are brought out to the patch area link1 link2 link3 link4 link5 link6 link7...

Page 127: ...d slot0 Figure 81 and figure 82 show the link patch area and the connections which need to be made to use the TMB16 as a master or slave board Figure 81 TMB16 Patch Area connections for master board r...

Page 128: ...onnector patch0 and would normally be connected to ConfigUp Also the board s PipeHead module0 link1 is taken to the edge connector at patch1 9 2 3 Summary of Network Configuration Figure 83 shows the...

Page 129: ...n the right and the switch is on when the slider is up and off when the slider is down The switch numbers and the on position are marked on the switch bank 9 3 1 Control Configuration The board s cont...

Page 130: ...4 IRQ DMA Selection The interrupt channel of the board may be selected using SW2 3 and 2 4 as follows The DMA channel of the board is fixed at channel 1 SW2 1 Description off Base address 150 hex defa...

Page 131: ...board In normal use they must both be off 9 4 The Edge Connector On the right hand edge of the TMB16 is a 37 way D type edge connector used for connection to other motherboards For this purpose the f...

Page 132: ...ctor is shown in figure 85 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 downAnalyse ConfigDown in PipeTail in subsystemError subsystemReset pat...

Page 133: ...sputer cards multi board where more than one TMB16 is used and link adaptor where the TMB16 is used as an interface between the PC and an external transputer board without any TRAMs on the TMB16 down...

Page 134: ...r system The first board is used as the master is controlled from the PC and provides the PC link interface whilst the second board is the slave The switches and link patch area for the first board sh...

Page 135: ...ure 87 Setup for slave in multi board operation SW1 SW2 Link patch area 1 2 3 4 OFF 1 2 3 4 OFF DN SU L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 UP DN SU L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 UP Master Sla...

Page 136: ...nto the C004 socket on the TMB16 Secondly a pipe jumper should be inserted into TRAM site 0 on the TMB16 not in the normal place for a pipe jumper but on the opposite side of the board as shown above...

Page 137: ...e 70 of the available bandwidth The following three subsections describe the operation of the host interface in detail 9 6 1 Operation of the Hardware The PC s Intel processor sees the TMB16 as two 16...

Page 138: ...with a string read instruction Clearly the operation of the interface depends on synchronization between the two processors When the Intel processor writes to the write port it cannot perform another...

Page 139: ...which is used during B004 interface emulation Essentially the register looks like a C012 as far as the PC is concerned On the transputer side it is mapped 16K ROM 32K Mapped to PC Flags 4K Internal Ra...

Page 140: ...rface The TMB16 supports DMA channel 1 and IRQ channels 3 default 7 Writing to the mode register in the PC s I O space determines whether the TMB16 works in full 16bit mode bit0 set to 0 or B004 B008...

Page 141: ...erred This is achieved by transmitting a single 16 bit counter That counter determines the number of bytes that follow In occam this protocol may be defined as INT16 BYTE i e the same as the iserver p...

Page 142: ...711 instruction Figure 92 summarizes the key software instructions used address bus memory transputer PC s Intel processor TMB16 PC Transputer network Key out in INSW OUTSW Memory mapper PC I O space...

Page 143: ...up to ten Transputer Modules The TMB17 is shipped with an IMSC004 link switch which provides for setting up user defined topologies The switch is flexible enough to allow any TRAM s link 0 or 3 to be...

Page 144: ...e drive and use the Browse dialog to select the file tps inf in the CD ROM directory win95 3 Click on OK After installation the I O base address and the interrupt used by the TMB17 can be determined o...

Page 145: ...mance interface This decouples the C012 link bandwidth limitations from the much faster PCI bus The high performance interface consists of 32bit access to the FIFO and transmit and receive FIFO level...

Page 146: ...fset 01h compatible with B004 standard software For higher performance the FIFO can be filled by WORD or DWORD writes to offset 1Ch The data should be written in the order to be send by the C012 link...

Page 147: ...6bit Word read should be used to read this register 10 3 2 7 Reset error Writing a one to bit 0 of offset 10h will force Reset to be sent to module 0 and the FIFO link interface a 0 must be written to...

Page 148: ...cted The links connected to the C004 are link0 of all TRAM slots except module0 module0 link0 is always connected to the host PC link3 of all TRAM slots link 0 of the T2 configuration processor eight...

Page 149: ...link1 link2 link3 link4 link5 link6 link7 link8 link9 link10 link11 link12 link13 link14 link15 link16 link17 link18 link19 link20 link21 link22 link23 link24 link25 link26 link27 link28 link29 modul...

Page 150: ...f the configuration processor PipeHead i e Module0 link1 two of the links from the crossbar switch C004L28 29 two links which are taken directly to the edge connector patch0 1 Figure 97 shows the link...

Page 151: ...therboard TMB M 711 Transputer Motherboard User Manual 143 C004 L29 patch1 slot0 link1 T2 Config patch0 C004 L28 Figure 98 TMB17 Patch Area connections for slave board root T2 C004 module0 L1 L3 L1 ed...

Page 152: ...nce 10 5 Description 10 5 1 Board Configuration The basic board configuration is achieved by the use of the configuration switches In the top left hand corner of the board there is a 4 way switch bank...

Page 153: ...S2 IBM source of control for module0 S3 MD0 source of control for modules1 to 9 If switch S3 is on then the source of control for modules1 to 9 is from the same source as module0 If S3 is off then mod...

Page 154: ...Connector On the left hand edge of the TMB17 is a 37 way D type edge connector On the TMB17 the edge connector is used for connection to other motherboards For this purpose the following are brought o...

Page 155: ...37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 downAnalyse ConfigDown in PipeTail in subsystemError subsystemReset patch link1out patch link0out...

Page 156: ...atch1 to C004 L29 The patch0 1 connections allow 10 links to be brought out from the C004 to the edge connector down subsystem ConfigDown PipeTail patch link1 patch link0 edge link7 edge link6 edge li...

Page 157: ...le TMB17 configured for use with an Inmos Toolset two TMB17s connected as a single system configured for use with an Inmos Toolset 10 6 1 Stand alone TMB17 The most common stand alone configuration fo...

Page 158: ...oard must be slaved to the other the default pipeline needs to be connected the configuration pipeline needs to be connected First set up one board with the same configuration as for stand alone opera...

Page 159: ...ns between the boards Switches Setting Description S1 off Use 20 Mbit s links S2 on Slot 0 controlled from UP S3 on Slots 1 to 9 controlled from same source as slot 0 Table 56 Settings for slave opera...

Page 160: ...Examples 152 Transputer Motherboard User Manual TMB M 711...

Page 161: ...toolset Solaris 2 device driver for the TMB14 TMB17 support for the PC Inquest tools TMB14 support for the Sun Inquest tools On line version of this manual 11 1 PC Installation The installation allows...

Page 162: ...RCE CPU 3CE If you are using a FORCE SPARCE CPU 3CE card please read this section carefully when selecting a VME base address for each VME Transputer board such as a TMB14 to be installed The FORCE SP...

Page 163: ...oard software on SPARC systems running Solaris 2 with a CD ROM drive 1 Log into the Sun as root 2 Put the supplied CD ROM into the CD ROM drive 3 Use volcheck to mount the CD ROM volcheck cdrom 4 Move...

Page 164: ...4s where the VME interface is disabled An entry in the configuration file consists of a list of the following properties terminated by a semi colon name The device driver name Must be set to tmb class...

Page 165: ...and TRAM modules installed as follows init 0 ok boot r Note that the r option is used to rebuild the device directories under devices and dev This must be done each time the configuration file is chan...

Page 166: ...t server utility Iserver The actual resource that the tool is to use is specified by the TRANSPUTER environment variable or command line arguments such as the Iserver sl option The name of the connect...

Page 167: ...Mmslink Reserved for future use Description Descriptive comment For example to use iserver on an ISA board at IO address 150 hex to load and run the transputer executable run btl use the command C ise...

Page 168: ...1 1 4K 1 4096K 3 1 T805d 25 1 75 1 0 2 2 1 4K 1 4096K 3 2 T805d 30 1 77 1 1 2 3 1 4K 1 4096K 3 3 T805d 25 1 79 1 2 2 4K 1 4096K 3 Interpretation of the output of check normally requires sketching a d...

Page 169: ...805b 25 1 75 1 0 2 4 1 4 T805b 25 1 75 1 3 2 5 1 5 T805b 25 1 75 1 4 2 In this case no link switch settings have been made To create a link 3 to link 0 pipeline between the TRAMs then C004 link 10 sho...

Page 170: ...ith the cfb option see the reference page to verify that the actual network is the same as that specified to the configurer 11 7 Transputer host I O utilities The following files are supplied in the t...

Page 171: ...TMB08 use either the default B004 compatible interface or the faster B008 compatible interface For a TMB17 PCI Motherboard 1 Add the following line to the ASERVDB database tmb17 txcs wtmb17 0 1 2 Set...

Page 172: ...when a time out error or signal has occurred write Writes to the link This function may return before the data transfer has completed or when a time out error or signal has occurred ioctl Perform var...

Page 173: ...open dev tmb 0 O_RDWR if fd 0 exit 1 Reset link io set op RESET io set val 0 if ioctl fd SETFLAGS io exit 1 The function ioctl can also be called with a request argument of READFLAGS with the third a...

Page 174: ...t outputs a list of the processors found and the connections between them The output of check can be used as the input of mtest ftest or load Alternatively the output from a previous run of check can...

Page 175: ...le h Print help page i Information tells you whats happening l name Use this link else use TRANSPUTER environment vari able m filename Use filename as a toolset map file n Do not reset the root transp...

Page 176: ...can be monitored using the n option where n is the number of a processor as defined in the output of check in the file filename as specified using the f option The host link connection to use is spec...

Page 177: ...ion with check which tests processors in a network of Transputers The host link connection to use is specified by the l option or the TRANSPUTER environment variable This corresponds to an entry in th...

Page 178: ...ces which iserver can use is kept in a file called the connection database The environment variable ICONDB should be set to the pathname of this file The resource that iserver should attempt to use is...

Page 179: ...y connects every interval seconds sz 1 2 Very verbose debug mode logs all transactions st Pass all of the following arguments to the booted pro gram Options and or arguments not recognised by iserver...

Page 180: ...or files onto a processor in a Transputer network The host link connection to use is specified by the l option or the TRANSPUTER environment variable This corresponds to an entry in the connection da...

Page 181: ...host link connection to use is specified by the l option or the TRANSPUTER environment variable This corresponds to an entry in the connection database pointed to by the environment variable ICONDB OP...

Page 182: ...Reference Manual Pages 174 Transputer Motherboard User Manual TMB M 711 0 Do not include root processor in tests h Display help page...

Page 183: ...he host The host connections can be connected another multiplexor giving rise to tree shaped structures which may be built up to any level of complexity A process accessing the host is referred to as...

Page 184: ...uts requests from the clients using a fair ALT This means that even if there is a continuous stream of requests from one client requests from any other client are guaranteed to be serviced within a fi...

Page 185: ...ut output HostOutput connect mult_1 HostInput to HostInput connect mult_1 HostOutput to HostOutput connect mult_1 Input 0 to mult_2 HostOutput connect mult_1 Output 0 to mult_2 HostInput connect mult_...

Page 186: ...rence Manual Pages 178 Transputer Motherboard User Manual TMB M 711 place mult_1 on TTM100_1 place mult_2 on TTM100_2 place HostInput on host place HostOutput on host FILES hostmux lku SEE ALSO iserve...

Page 187: ...0 cache block size val DEFAULT_BLOCK 16384 process stacksize 10K heapsize 1M interface input from_host output to_host input from_client n output to_client n int num_chans n int io_type type int packet...

Page 188: ...ined in the above value declarations packet_size is used to determine the size of iserver packets when the io_type is BIG_IO it is ignored for all other I O types To obtain I O compatible with a stand...

Page 189: ...low level file I O functions Several tech niques are included that give optimal results on different kinds of hardware This is done by allowing a larger iserver packet size up to 4096 bytes to be use...

Page 190: ...d a secon dary parameter The parameter is ignored unless otherwise specified The following I O types can be used STD_IO Standard mode default TMB16_IO Optimize I O for the TMB16 NB the calling process...

Page 191: ...es cannot be multiplexed using so multiplexor or buffered using so buffer If TMB16 optimized I O is enabled the calling process must have its host channels connected DIRECTLY to the TMB16 interface li...

Page 192: ...Reference Manual Pages 184 Transputer Motherboard User Manual TMB M 711...

Page 193: ...all of the transputers then it is best to draw a picture of the processors and links that are detected Then you can determine which processors or links are not detected The following checklist based o...

Page 194: ...Check the settings of the link patch area and cable connections Using a continuity tester or resistance meter check the connection of the link There should be a 56 Ohm series resistance If a transput...

Page 195: ...ime resolving any clashes that occur If you are using more than one transputer card start with just one card then introduce the others You may need to change the IO address of the transputer card Reme...

Page 196: ...PC Host Interface 188 Transputer Motherboard User Manual TMB M 711...

Page 197: ...ation File 156 configuration pipeline 13 24 Connection database 158 control architecture 9 Control configuration TMB03 37 TMB04 49 crossbar switches 13 D Device Driver 164 Device File 157 Diagnostics...

Page 198: ...server 158 162 170 L large TRAM 10 link cable 12 Link patch area TMB08 60 TMB14 104 TMB17 141 Link speed TMB03 38 TMB12 76 TMB14 102 link switches 13 load 172 M man 163 master 19 memory teste 159 MMS...

Page 199: ...guration 58 Link patch area 60 67 TMB12 73 board layout 75 C004 connections 85 configuration processor 84 control selection 76 Electronic Link Switching 82 Error Lights 81 K1 Jumpers 86 link speed sel...

Page 200: ...162 Hedgehog 125 host interface 129 IRQ DMA 122 link adaptor setup 128 link patch area 118 Link speed 122 slave setup 126 stand alone 126 TMB17 135 Aserver support 163 Control configuration 145 Edge c...

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